Skip to main content

SOM-SMARC-Genio510 / Genio700

Generals​

image-20240216-143606.png

Description​

The Wilk is powered by MediaTek Genio 700 or MediaTek Genio 510 Applications Processor. They are designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power.

The Genio 510 features advanced implementation of a dual ARM® Cortex®-A78 core, which operates at speeds of up to 2.0GHz and four ARM® Cortex®-A55 core, which operates at speeds of up to 2.0GHz

The Genio 700 features advanced implementation of a dual ARM® Cortex®-A78 core, which operates at speeds of up to 2.2GHz and six ARM® Cortex®-A55 core, which operates at speeds of up to 2.0GHz.

An Mali G57 MC3 GPU is also integrated as Cadence Tensilica VP6 with MediaTek APU3.0 for AI Acceleration.

A 64-bit LPDDR4 interface is used for memory. There are a number of other interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

  • eMMC (up to 64 GByte)

  • upto 2x 1Gbit Ethernet

  • TPM

  • 1x USB 3.1 2x USB 2.0

  • MIPI/eDP, HDMI/DP

  • RTC

  • EEPROM

  • WLAN 802.11 a/b/g/n/ac and BT 5.3 Combo module (M.2 1216)

SMARC Standard​

The SMARC ("Smart Mobility ARChitecture") is a versatile small form factor computer Module definition targeting applications that require low power, low costs, and high performance. The Modules will typically use ARM SOCs similar or the same as those used in many familiar devices such as tablet computers and smart phones. Alternative low power SOCs and CPUs, such as tablet oriented x86 devices and other RISC CPUs may be used as well. The Module power envelope is typically under 6W although designs up to about 15W are possible.

Block Diagram​

Features and Interfaces

Features​

Processor​

MediaTek Genio 700 ARM® Octa-core CPU (Dual Cortex-A78 @ 2.2 GHz and Six Cortex-A55 @ 2.0 GHz) MediaTek Genio 510 ARM® Six-core CPU (Dual Cortex-A78 @ 2.0 GHz and Four Cortex-A55 @ 2.0 GHz) Mali G57 MC3 GPU AI Accelerator: Cadence Tensilica VP6 with MediaTek APU3.0 System Companion Chip: MDSP RV55 DSP: Cadence Tensilica HiFi5

Memory​

Up to 8GByte of 64-bit LPDDR4-4000

Storage​

Up to 64 GByte eMMC

Wireless​

WLAN 802.11 a/b/g/n/ac/ax BT 5.3 MicroRF-antenna connector

Power​

PMIC to generate all internal and external voltages from 3.3V up to 5V supply.

Dimensions​

(Length x Width x Height): 82.0 x 50.0 x 5.4 mm

Interfaces / Signals accessible over connector​

  • Power Supply through 5.0VDC +- 5%, +3.2V_RTC

  • LVDS Dual Channel or eDP (factory alternatives) up to 2560x1600p60

  • HDMI or DP (factory alternatives) up to 4K60

  • SD 4-bit interface (boot device)1

  • 2x Gigabit Ethernet interfaces

  • 1x USB 2.0 OTG port

  • up to 4x USB 2.0 using optional internal 2.0 Hub

  • 1x I2S port

  • 2x UART (4-wires)

  • 2x UART (2-wires)

  • 1x CAN interfaces (via SPI CAN Controller)

  • 13x GPIOs

  • 1 x MIPI_CSI0 2 Lanes Camera interface

  • 1 x MIPI_CSI1 4 Lanes Camera Interface

  • 1x General Purpose I2C Bus

  • 2x PWM ports

  • TPM

Technical Documents

1. Pin description

The main connector of the WILK is the J2800 SMARC connector. J500 may be used for debugging, programming and testing. On the top side are UFL antenna connectors for the on-board WLAN + BT chip.

1.1 Pin description​

The following signals are present at the SMARC connector.

Table 1: J2800: SMARC connector​

SignalPinPinSignal
S1I2C6_SCL
SMB_ALERT#P1S2I2C6_SDA
GNDP2S3GND
CSI1_CK_PP3S4-
CSI1_CLK_NP4S5I2C5_SCL
-P5S6-
-P6S7I2C5_SDA
CSI1_RX0_PP7S8CSI0_CK_P
CSI1_RX0_NP8S9CSI0_CK_N
GNDP9S10GND
CSI1_RX1_PP10S11CSI0_RX0_P
CSI1_RX1_NP11S12CSI0_RX0_N
GNDP12S13GND
CSI1_RX2_PP13S14CSI0_RX1_P
CSI1_RX2_NP14S15CSI0_RX1_N
GNDP15S16GND
CSI1_RX3_PP16S17GBE1_MDIO_P
CSI1_RX3_NP17S18GBE1_MDIO_N
GNDP18S19GBE1_LINK100#
GBEO_MDI3_NP19S20GBE1_MDI1_P
GBEO_MDI3_PP20S21GBE1_MDI1_N
GBEO_LINK100#P21S22-
GBEO_LINK1000#P22S23-
GBEO_MDI2_NP23S24-
GBEO_MDI2_PP24S25GND
GBEO_LINK_ACT#P25S26-
GBEO_MDI1_NP26S27-
GBEO_MDI1_PP27S28USB_VDD33A
-P28S29-
GBEO_MDI0_NP29S30-
GBEO_MDI0_PP30S31GBE1_LINK_ACT#
-P31S32-
GNDP32S33-
-P33S34GND
SDIO_CMDP34S35USB4_DP
SDIO_CD#P35S36USB4_DN
SDIO_CKP36S37
SDIO_PWR_EN_3V3P37S38I2SO_MCK
GNDP38S39I2S0_LRCK
SDIO_D0P39S40-
SDIO_D1P40S41I2S0_SDIN
SDIO_D2P41S42I2S0_CK
SDIO_D3P42S43-
SPIO_CS0#P43S44-
SPIO_CKP44S45-
SPIO_DINP45S46-
SPIO_DOP46S47GND
GNDP47S48I2C_GP_CK
-P48S49I2C_GP_DAT
-P49S50I2S2_LRCK
GNDP50S51I2S2_SDOUT
-P51S52-
-P52S53I2S2_CK
GNDP53S54-
ESPI_CS0#P54S55USB5_EN_OC#
-P55S56ESPI_IO_2
ESPI_CKP56S57ESPI_IO_3
ESPI_IO_1P57S58-
ESPI_IO_0P58S59USB5_DP
GNDP59S60USB5_DN
USB0_DPP60S61GND
USB0_DNP61S62
USB0_EN_OC#P62S63
USB0_VBUS_DETP63S64GND
USB0_OTG_IDP64S65
USB1_DPP65S66
USB1_DNP66S67GND
USB1_EN_OC#P67S68USB3_DP
GNDP68S69USB3_DN
USB2_DPP69S70GND
USB2_DNP70S71USB2_SS_TXP
USB2_EN_OC#P71S72USB2_SS_TXN
STM32_RST#P72S73GND
-P73S74USB2_SS_RXP
USB3_EN_OC#P74S75USB2_SS_RXN
EXT_PCIE_A_RST#P75S76-
USB4_EN_OC#P76S77-
PCIE_B_CKREQ#P77S78-
PCIE_A_CKREQ#_CONP78S79-
GNDP79S80GND
-P80S81-
-P81S82-
GNDP82S83GND
REF_CLKP_CARRIERP83S84-
REF_CLKN_CARRIERP84S85-
GNDP85S86GND
PCIE_RXP_CARRIERP86S87-
PCIE_RXN_CARRIERP87S88-
GNDP88S89GND
PCIE_TXP_CARRIERP89S90-
PCIE_TXN_CARRIERP90S91-
GNDP91S92GND
HDMI_D2+P92S93DP0_LANE0+
HDMI_D2-P93S94DP0_LANE0-
GNDP94S95DP0_AUX_SEL
HDMI_D1+P95S96DP0_LANE1+
HDMI_D1-P96S97DP0_LANE1-
GNDP97S98DP0_HPD_EXT
HDMI_D0+P98S99DP0_LANE2+
HDMI_D0-P99S100DP0_LANE2-
GNDP100S101GND
HDMI_CK+P101S102DP0_LANE3+
HDMI_CK-P102S103DP0_LANE3-
GNDP103S104
HDMI_HPD_EXTP104S105DP0_AUX+
HDMI_CTRL_CKP105S106DP0_AUX-
HDMI_CTRL_DATP106S107LCD1_BKLT_EN
DP1_AUX_SELP107S108LVDS1_EDP_CLK_P
GPIO0/CAM0_PWR#P108S109LVDS1_EDP_CLK_N
GPIO1/CAM1_PWR#P109S110GND
GPIO2/CAM0_RST#P110S111LVDS1_EDP_D0_P
GPIO3/CAM1_RST#P111S112LVDS1_EDP_D0_N
GPIO4P112S113EDP1_HPD_EXT
GPIO5P113S114LVDS1_EDP_D1_P
GPIO6P114S115LVDS1_EDP_D1_N
GPIO7P115S116LCD1_VDD_EN
GPIO8P116S117LVDS1_TX2_P
GPIO9P117S118LVDS1_TX2_N
GPIO10P118S119GND
GPIO11P119S120LVDS1_TX3_P
GNDP120S121LVDS1_TX3_N
I2C_PM_CKP121S122LCD1_BKLT_PWM
I2C_PM_DATP122S123GPIO13
BOOT_SEL0#P123S124GND
BOOT_SEL1#P124S125LVDS0_TX0_P
BOOT_SEL2#P125S126LVDS0_TX0_N
RESET_OUT#P126S127LCD0_BKLT_EN
RESET_IN#P127S128LVDS0_TX1_P
POWER_BTN#P128S129LVDS0_TX1_N
SER0_TXP129S130GND
SER0_RXP130S131LVDS0_TX2_P
SER0_RTS#P131S132LVDS0_TX2_N
SER0_CTS#P132S133LCD0_VDD_EN
GNDP133S134LVDS0_CK_P
SER1_TXP134S135LVDS0_CK_N
SER1_RXP135S136GND
SER2_TXP136S137LVDS0_TX3_P
SER2_RXP137S138LVDS0_TX3_N
SER2_RTS#P138S139I2C0_SCL
SER2_CTS#P139S140I2C0_SDA
SER3_TXP140S141LVDS0_BKLT_PWM
SER3_RXP141S142GPIO12
GNDP142S143GND
CAN0_TXP143S144EDP0_HPD
CAN0_RXP144S145WDT_TIME_OUT#
P145S146EXT_PCIE_WAKE#
P146S147VDD_RTC
5V_SLEEPP147S148LID#
5V_SLEEPP148S149SLEEP#
5V_SLEEPP149S150VIN_PWR_BAD#
5V_SLEEPP150S151CHARGING#
5V_SLEEPP151S152CHARGER_PRSNT#
5V_SLEEPP152S153CARRIER_STBY#
5V_SLEEPP153S154CARRIER_PWR_ON
5V_SLEEPP154S155FORCE_RECOV#
5V_SLEEPP155S156BATLOW#
5V_SLEEPP156S157TEST#
S158GND

Table 2: J500: GENIO 700 JTAG connector:​

This flex-cable connector uses the SMARC JTAG connector standard.

PinSignal
11V8_RUN_PTC
2JTAG_TRST#
3JTAG_TMS
4JTAG_TDO
5JTAG_TDI
6JTAG_TCK
7-
81V8_RUN_PTC (10K pullup)
9(10K pulldown)
10GND

1.2 Electrical pin information​

PI:Power InputDO:Digital Output
PO:Power OutputDIO:Digital Input/Output
DDI:Differential Input
AI:Analog InputDDO:Differential Output
AO:Analog OutputDDIO:Differential Input/Output
DI:Digital InputODOpen-Drain Output
PD:Pull-Down(PDp: Pull-Down, Pull-behavior can be changed by software)
PU:Pull-UpPUp: Pull-Up, Pull-behavior can be changed by software

If two "types" are specified, the first value determines the type of primary function.

Table 3: SMARC pin information​

PinNameTypeVoltageConnected to
P1SMB_ALERT#DI, PU(10K)1V8STM32, pin M2, port PA5
P2GNDGround
P3CSI1_CK_PDDI1V2GENIO 700
P4CSI1_CLK_NDDI1V2GENIO 700
P5-
P6-
P7CSI1_RX0_PDDI1V2GENIO 700
P8CSI1_RX0_NDDI1V2GENIO 700
P9GNDGround
P10CSI1_RX1_PDDI1V2GENIO 700
P11CSI1_RX1_NDDI1V2GENIO 700
P12GNDGround
P13CSI1_RX2_PDDI1V2GENIO 700
P14CSI1_RX2_NDDI1V2GENIO 700
P15GNDGround
P16CSI1_RX3_PDDI1V2GENIO 700
P17CSI1_RX3_NDDI1V2GENIO 700
P18GNDGround
P19GBEO_MDI3_NDDIO3V3Gbit Ethernet-Phy
P20GBEO_MDI3_PDDIO3V3Gbit Ethernet-Phy
P21GBEO_LINK100#DO, PU(10K)3V3Gbit Ethernet-Phy
P22GBEO_LINK1000#DO, PU(4K7)3V3Gbit Ethernet-Phy
P23GBEO_MDI2_NDDIO3V3Gbit Ethernet-Phy
P24GBEO_MDI2_PDDIO3V3Gbit Ethernet-Phy
P25GBEO_LINK_ACT#DO, PU(10K)3V3Gbit Ethernet-Phy
P26GBEO_MDI1_NDDIO3V3Gbit Ethernet-Phy
P27GBEO_MDI1_PDDIO3V3Gbit Ethernet-Phy
P28-
P29GBEO_MDI0_NDDIO3V3Gbit Ethernet-Phy
P30GBEO_MDI0_PDDIO3V3Gbit Ethernet-Phy
P31-
P32GNDGround
P33-
P34SDIO_CMDDO; PU(10K)1V8 or 3V3GENIO 700
P35SDIO_CD#DI, PU(10K)1V8 or 3V3GENIO 700
P36SDIO_CKDO1V8 or 3V3GENIO 700
P37SDIO_PWR_EN_3V3DO3V3GENIO 700
P38GNDGround
P39SDIO_D0DIO1V8 or 3V3GENIO 700
P40SDIO_D1DIO1V8 or 3V3GENIO 700
P41SDIO_D2DIO1V8 or 3V3GENIO 700
P42SDIO_D3DIO1V8 or 3V3GENIO 700
P43SPIO_CS0#DO1V8GENIO 700
P44SPIO_CKDO1V8GENIO 700
P45SPIO_DINDI1V8GENIO 700
P46SPIO_DODO1V8GENIO 700
P47GNDGround
P48-
P49-
P50GNDGround
P51-
P52-
P53GNDGround
P54ESPI_CS0#DO1V8GENIO 700
P55-
P56ESPI_CKDO1V8GENIO 700
P57ESPI_IO_1DIO1V8GENIO 700
P58ESPI_IO_0DIO1V8GENIO 700
P59GNDGround
P60USB0_DPDDIO3V3GENIO 700
P61USB0_DNDDIO3V3GENIO 700
P62USB0_EN_OC#DI,DO,PU(10K)3V3STM32, pin K1, port PC0
P63USB0_VBUS_DETDI, PD(10K)3V3GENIO 700
P64USB0_OTG_IDDI3V3GENIO 700
P65USB1_DPDDIO3V3USB Hub or
GENIO 700 (if no USB Hub)
P66USB1_DNDDIO3V3USB Hub or
GENIO 700 (if no USB Hub)
P67USB1_EN_OC#DI,DO,PU(10K)3V3STM32, pin K2, port PC2
P68GNDGround
P69USB2_DPDDIO3V3USB Hub (optional)
P70USB2_DNDDIO3V3USB Hub (optional)
P71USB2_EN_OC#DI,DO,PU3V3USB Hub (optional)
P72STM32_RST#DI, PU(10K)1V8STM32, pin G2
P73-
P74USB3_EN_OC#DI,DO,PU(10K)3V3STM32, pin M1, port PA2
P75EXT_PCIE_A_RST#D01V8GENIO 700
P76USB4_EN_OC#DI,DO,PU3V3USB Hub (optional)
P77PCIE_B_CKREQ#DI, DO1V8STM32, pin C11, port PA13
used as SWDIO
P78PCIE_A_CKREQ#DI1V8STM32, pin B12
used as SWCLK
P79GNDGround
P80-
P81-
P82GNDGround
P83REF_CLKP_CARRIERDD01V8GENIO 700
P84REF_CLKN_CARRIERDD01V8GENIO 700
P85GNDGround
P86PCIE_RXP_CARRIERDDI1V8GENIO 700
P87PCIE_RXN_CARRIERDDI1V8GENIO 700
P88GNDGround
P89PCIE_TXP_CARRIERDDO1V8GENIO 700
P90PCIE_TXN_CARRIERDDO1V8GENIO 700
P91GNDGround
P92HDMI_D2+DDO1V8GENIO 700
P93HDMI_D2-DDO1V8GENIO 700
P94GNDGround
P95HDMI_D1+DDO1V8GENIO 700
P96HDMI_D1-DDO1V8GENIO 700
P97GNDGround
P98HDMI_D0+DDO1V8GENIO 700
P99HDMI_D0-DDO1V8GENIO 700
P100GNDGround
P101HDMI_CK+DDO1V8GENIO 700
P102HDMI_CK-DDO1V8GENIO 700
P103GNDGround
P104HDMI_HPDPD (1M)1V8GENIO 700
P105HDMI_CTRL_CKPD (100K)1V8GENIO 700
P106HDMI_CTRL_DATPD (100K)1V8GENIO 700
P107DP1_AUX_SELPD (1M)not connected
P108GPIO0/CAM0_PWR#DIO1V8GENIO 700
P109GPIO1/CAM1_PWR#DIO1V8GENIO 700
P110GPIO2/CAM0_RST#DIO1V8GENIO 700
P111GPIO3/CAM1_RST#DIO1V8GENIO 700
P112GPIO4DIO1V8STM32, Pin M8, Port PE8
P113GPIO5DIO1V8STM32, Pin K8, Port PE9
P114GPIO6DIO1V8STM32, Pin L8, Port PE10
P115GPIO7DIO1V8STM32, Pin M9, Port PE11
P116GPIO8DIO1V8STM32, Pin L9, Port PE12
P117GPIO9DIO1V8STM32, Pin M10, Port PE13
P118GPIO10DIO1V8STM32, Pin K9, Port PE14
P119GPIO11DIO1V8STM32, Pin L10, Port PE15
P120GNDGround
P121I2C_PM_CKDO, PU(4K7)1V8STM32, Pin C4, Port PB6
GENIO 700
P122I2C_PM_DATDIO, PU(4K7)1V8STM32, Pin B3 Port PB7
GENIO 700
P123BOOT_SEL0#DI, PU(10K)1V8STM32, Pin L11, Port PB11
P124BOOT_SEL1#DI, PU(10K)1V8STM32, Pin M12, Port PB13
P125BOOT_SEL2#DI, PU(10K)1V8STM32, Pin L12, Port PA8
P126RESET_OUT#DO1V8STM32, Pin K12, Port PC7
P127RESET_IN#DI, PU(10K)1V8STM32, Pin G11, Port PD11
P128POWER_BTN#DI, PU(10K)1V8STM32, Pin E10, Port PA10
P129SER0_TXDO1V8GENIO 700
P130SER0_RXDI, PU(100K)1V8GENIO 700
P131SER0_RTS#DO1V8GENIO 700
P132SER0_CTS#DI, PU(100K)1V8GENIO 700
P133GNDGround
P134SER1_TXDO1V8GENIO 700
P135SER1_RXDI, PU(100K)1V8GENIO 700
P136SER2_TXDO1V8GENIO 700 (optional)
P137SER2_RXDI, PU(100K)1V8GENIO 700 (optional)
P138SER2_RTS#DO1V8GENIO 700 (optional)
P139SER2_CTS#DI, PU(100K)1V8GENIO 700 (optional)
P140SER3_TXDO1V8GENIO 700
P141SER3_RXDI, PU(100K)1V8GENIO 700
P142GNDGround
P143CAN0_TXDO1V8CAN controller
P144CAN0_RXDI1V8CAN controller
P145
P146
P1475V_SLEEPPI5V0
P1485V_SLEEPPI5V0
P1495V_SLEEPPI5V0
P1505V_SLEEPPI5V0
P1515V_SLEEPPI5V0
P1525V_SLEEPPI5V0
P1535V_SLEEPPI5V0
P1545V_SLEEPPI5V0
P1555V_SLEEPPI5V0
P1565V_SLEEPPI5V0
S1I2C6_SCLDO, PU(4K7)1V8GENIO 700
S2I2C6_SDADIO, PU(4K7)1V8GENIO 700
S3GNDGround
S4-
S5I2C5_SCLDO, PU(4K7)1V8GENIO 700
S6-
S7I2C5_SDADIO, PU(4K7)1V8GENIO 700
S8CSI0_CK_PDDI1V2GENIO 700
S9CSI0_CK_NDDI1V2GENIO 700
S10GNDGround
S11CSI0_RX0_PDDI1V2GENIO 700
S12CSI0_RX0_NDDI1V2GENIO 700
S13GNDGround
S14CSI0_RX1_PDDI1V2GENIO 700
S15CSI0_RX1_NDDI1V2GENIO 700
S16GNDGround
S17GBE1_MDIO_PDDIO, PU(49R9)USB_VDD33ALAN9514
S18GBE1_MDIO_NDDIO, PU(49R9)USB_VDD33ALAN9514
S19GBE1_LINK100#DOUSB_VDD33ALAN9514
S20GBE1_MDI1_PDDIO, PU(49R9)USB_VDD33ALAN9514
S21GBE1_MDI1_NDDIO, PU(49R9)USB_VDD33ALAN9514
S22-
S23-
S24-
S25GNDGround
S26-
S27-
S28USB_VDD33A
S29-
S30-
S31GBE1_LINK_ACT#DOUSB_VDD33ALAN9514
S32-
S33-
S34GNDGround
S35USB4_DPDDIO3V3USB Hub (optional)
S36USB4_DNDDIO3V3USB Hub (optional)
S37
S38I2SO2_MCKDO1V8GENIO 700
S39I2S0_LRCKDIO1V8GENIO 700
S40-
S41I2S0_SDINDI1V8GENIO 700
S42I2S0_CKDO1V8GENIO 700
S43-
S44-
S45-
S46-
S47GNDGround
S48I2C_GP_CKDO, PU(4K7)1V8GENIO 700
S49I2C_GP_DATDIO, PU(4K7)1V8GENIO 700
S50I2S2_LRCKDIO1V8GENIO 700
S51I2S2_SDOUTDO1V8GENIO 700
S52-
S53I2S2_CKDO1V8GENIO 700
S54-
S55USB5_EN_OC#DI,DO,PU3V3USB Hub (optional)
S56ESPI_IO_2DIO1V8GENIO 700
S57ESPI_IO_3DIO1V8GENIO 700
S58-
S59USB5_DPDDIO3V3USB Hub (optional)
S60USB5_DNDDIO3V3USB Hub (optional)
S61GNDGround
S62
S63
S64GNDGround
S65
S66
S67GNDGround
S68USB3_DPDDIO3V3GENIO 700
S69USB3_DNDDIO3V3GENIO 700
S70GNDGround
S71USB2_SS_TXPDDOGENIO 700
S72USB2_SS_TXNDDOGENIO 700
S73GNDGround
S74USB2_SS_RXPDDIGENIO 700
S75USB2_SS_RXNDDIGENIO 700
S76-
S77-
S78-
S79-
S80GNDGround
S81-
S82-
S83GNDGround
S84-
S85-
S86GNDGround
S87-
S88-
S89GNDGround
S90-
S91-
S92GNDGround
S93DP0_LANE0+DDO1V8GENIO 700
S94DP0_LANE0-DDO1V8GENIO 700
S95DP0_AUX_SELPD(1M)not connected
S96DP0_LANE1+DDO1V8GENIO 700
S97DP0_LANE1-DDO1V8GENIO 700
S98DP0_HPD_EXTDI1V8GENIO 700
S99DP0_LANE2+DDO1V8GENIO 700
S100DP0_LANE2-DDO1V8GENIO 700
S101GNDGround
S102DP0_LANE3+DDO1V8GENIO 700
S103DP0_LANE3-DDO1V8GENIO 700
S104
S105DP0_AUX+DDO, PD(100K)3V3GENIO 700
S106DP0_AUX-DDO, PU(100K)3V3GENIO 700
S107LCD1_BKLT_ENDO1V8GENIO 700
S108LVDS1_EDP_CLK_PDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S109LVDS1_EDP_CLK_NDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S110GNDGround
S111LVDS1_EDP_D0_PDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S112LVDS1_EDP_D0_NDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S113EDP1_HPD_EXTDI, PD(1M)1V8GENIO 700
S114LVDS1_EDP_D1_PDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S115LVDS1_EDP_D1_NDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S116LCD1_VDD_ENDO1V8GENIO 700
S117LVDS1_TX2_PDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S118LVDS1_TX2_NDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S119GNDGround
S120LVDS1_TX3_PDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S121LVDS1_TX3_NDDO1V8MIPI to LVDS bridge
or GENIO 700 eDP
S122LCD1_BKLT_PWMDO1V8GENIO 700
S123GPIO13DIO1V8STM32, Pin E11, Port PD14
S124GNDGround
S125LVDS0_TX0_PDDIO1V8MIPI to LVDS bridge
S126LVDS0_TX0_NDDIO1V8MIPI to LVDS bridge
S127LVDS0_BKLT_ENDO1V8GENIO 700
S128LVDS0_TX1_PDDIO1V8MIPI to LVDS bridge
S129LVDS0_TX1_NDDIO1V8MIPI to LVDS bridge
S130GNDGround
S131LVDS0_TX2_PDDIO1V8MIPI to LVDS bridge
S132LVDS0_TX2_NDDIO1V8MIPI to LVDS bridge
S133LVDS0_VDD_ENDO1V8GENIO 700
S134LVDS0_CK_PDDIO1V8MIPI to LVDS bridge
S135LVDS0_CK_NDDIO1V8MIPI to LVDS bridge
S136GNDGround
S137LVDS0_TX3_PDDIO1V8MIPI to LVDS bridge
S138LVDS0_TX3_NDDIO1V8MIPI to LVDS bridge
S139I2C0_SCLDO, PU(4K7)1V8GENIO 700
S140I2C0_SDADIO, PU(4K7)1V8GENIO 700
S141LVDS0_BKLT_PWMDO1V8GENIO 700
S142GPIO12DIO1V8STM32, Pin E12, Port PD13
S143GNDGround
S144EDP0_HPDPD(1M)not connected
S145WDT_TIME_OUT#DO1V8STM32, Pin J11, Port PC6
S146EXT_PCIE_WAKE#DI1V8GENIO 700
S147VDD_RTCPI3V0
S148LID#DI, PU(10K)1V8STM32, Pin D12, PA11
S149SLEEP#DI, PU(10K)1V8STM32, Pin C12, PA12
S150VIN_PWR_BAD#DIPower management
S151CHARGING#DI, PU(10K)1V8STM32, Pin D10, Port PF8
S152CHARGER_PRSNT#DI, PU(10K)1V8STM32, Pin H11, Port PD9
S153CARRIER_STBY#DO1V8STM32, Pin M4, Port PC5
S154CARRIER_PWR_ONDO1V8STM32, Pin L3, Port PA4
S155FORCE_RECOV#DI, PU(10K)1V8STM32, Pin H12, Port PD10
S156BATLOW#DI, PU(10K)1V8STM32, Pin B11, Port PA15
S157TEST#DI, PU(10K)1V8STM32, Pin L2, Port PA1
S158GNDGround

2. Interfaces

This chapter includes a short description of all interfaces of the WILK. Please consult the processor datasheet for detailed information.

2.1 Power Supply​

The WILK can be supplied by a single +5.0V power supply.

Table 4: Power Supply pins​

NameDescription
5V_SLEEP5V power input. This supply controls the STM32. STM32 MCU controls
reset and power to the GENIO 700 processor.
GNDGround input
VDD_RTC3V power supply to supply the RTC on the WILK

2.2 Control signals​

Table 5: Control Signal pins​

NameDescription
RESET_IN#Negated reset input. 0: reset device, 1: normal operation
RESET_OUT#Negated reset output. 0: device in reset, 1: normal operation
(active low)
BOOT_SEL[2…0]tell the module what physical device to do a BCT boot from, not
used!The boot device selection for the WILK is done via assembly options. A
distinction is only made between booting from SPI NOR flash or eMMC
(standard).
STM32_RST#Negated reset input for STM32. 0: reset STM32, 1: normal operation
(active low)
POWER_BTN#Carrier based power button (active low)
WDT_TIME_OUT#Watchdog output (active low)
LID#Lid open/close indication input (active low)
SLEEP#Sleep indicator input (active low)
VIN_PWR_BAD#Power status input. 0: Carrierrboard power is not ready to
support WILK
1: Carrierboard power is ready to support WILK (active low)
CHARGING#Input, held low by carrier during battery scharging, float when
charging is complete (active low)
CHARGER_PRSNT#Input, held low by Carrier if DC input for battery charger is
present (active low)
CARRIER_STBY#Power status output. If the power save state standby
mode is implemented at the Carrier the runtime voltage rails are enabled with
this control signal from the module. The module drives this signal high to
enable runtime power rails. If no separate standby mode is implemented all
rails are enabled with CARRIER_PWR_ON signal. This signal is driven high by
the module at runtime. (active low)
CARRIER_PWR_ONPower status output. It is a signal to Carrier that the
Carrier specific power supplies that shall be powered during standby may be
enabled. If standby power save state is implemented at the Carrier this signal
enables the standby voltage rails.
FORCE_RECOV#Primary boot media can be re-initialized (active low)
BATLOW#Input, battery low indication to Module. Carrier to float the line in
inactive state (active low)
TEST#Negated test input of STM32. 0: device in programming mode, 1: normal
operation (active low)

2.3 UART​

The GENIO 700 provides 4 Universal Asynchronous Receiver/Transmitter. With a transceiver these signals can be converted to RS232, RS485 or IrDA.

Following UART ports are accessible through the SMARC connector:

Table 7: UART pins​

NameDescription
SER0_TXSerial 0 transmit output
SER0_RXSerial 0 receive input
SER0_RTS#Serial 0 request to send output (active low)
SER0_CTS#Serial 0 clear to send input (active low)
SER1_TXSerial 1 transmit output
SER1_RXSerial 1 receive input
SER2_TXSerial 2 transmit output
SER2_RXSerial 2 receive input
SER2_RTS#Serial 2 request to send output (active low)
SER2_CTS#Serial 2 clear to send input (active low)
SER3_TXSerial 3 transmit output
SER3_RXSerial 3 receive input

Baudrate: High-speed TIA/EIA-232-F compatible, up to 1Mbit/s, IrDA-compatible, up to 115.2 Kbit/s

Data-Bits: 7 or 8 bits (RS232) or 9 bit (RS485)

Stop Bits: 1, 2

Parity: None, Even, Odd

Features: Hardware flow control (RTS, CTS)

2.4 SPI​

The Serial Peripheral Interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals.

Table 8: SPI pins​

NameDescription
SPIO_CS0#SPI 0 slave select
SPI0_CKSPI 0 clock
SPI0_DINSPI 0 data in
SPI0_DOSPI 0 data out

Speed: up to xxx MHz

2.5 eSPI​

The enhanced Serial Peripheral Interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals.

Table 8: SPI pins​

NameDescription
ESPI_CS0#eSPI slave select
ESPI_CKeSPI clock
ESPI_IO_0eSPI data 0 in/out
ESPI_IO_1eSPI data 1 in/out
ESPI_IO_2eSPI data 2 in/out
ESPI_IO_3eSPI data 3 in/out

2.6 I2C​

The Inter-Integrated Circuit (I2C ) provides functionality of a standard I2C master and slave.

Table 9: I2C pins​

NameDescription
I2C0_SCLI2C0 clock
I2C0_SDAI2C0 data
I2C3_SCLI2C3 clock
I2C3_SDAI2C3 data
I2C_GP_CKI2C GP clock
I2C_GP_DATI2C GP data
I2C5_SCLI2C5 clock
I2C5_SDAI2C5 data
I2C_PM_CKI2C PM clock
I2C_PM_DATI2C PM data

Speed: Standard mode, up to 100kbit/s Fast mode, up to 400 kbit/s

Features: Multimaster operation. I2C Bus specification version 2.1

2.7 I2S​

The Inter-IC sound interface provides a synchronous audio interface (SAI) and is used to connect to audio codecs.

Table 10: I2S pins​

NameDescription
I2S0_LRCKI2S0 Left & Right Synchronisation Clock
I2S0_SDINI2S0 Digital Audio Input
I2S0_CKI2S0 Digital Audio Clock
I2S2_LRCKI2S2 Left & Right Synchronisation Clock
I2S2_SDOUTI2S2 Digital Audio Output
I2S2_CKI2S2 Digital Audio Clock

2.8 SDIO​

The SDIO interface may be used to connect a SD-Card, eMMC or SDIO hardware.

Table 11: SDIO pins​

NameDescription
SDIO_CMDSDIO command output
SDIO_CD#SDIO card detect input (active low)
SDIO_CKSDIO clk output
SDIO_PWR_EN_3V3SDIO Power enable signal
SDIO_D0SDIO data bit 0
SDIO_D1SDIO data bit 1
SDIO_D2SDIO data bit 2
SDIO_D3SDIO data bit 3

Speed: Card bus clock frequency up to 208 MHz

Features: Conforms to the SD Host Controller Standard Specification version 3.0.

Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/5.0. Compatible with the SD Memory Card Specification version 3.0 and supports the Extended Capacity SD Memory Card Compatible with the SDIO Card Specification version 3.0

2.9 USB​

In the standard configuration, the WILK offers one USB 3.1 port and two USB 2.0 ports, which are routed to the SMARC connector. As an assembly option, a quad USB hub is possible, so that up to five USB ports are possible on the SMARC connector.

Table 12: USB pins​

NameDescription
USB0_DPUSB Port 0 data (positive), USB2.0
USB0_DNUSB Port 0 data (negative), USB2.0
USB0_EN_OC#USB Port 0 power enable output and overcurrent input (active low)
USB0_VBUS_DETUSB Port 0 VBUS detection
USB0_OTG_IDUSB Port 0 ID detect
USB1_DPUSB Port 1 data (positive), USB2.0
USB1_DNUSB Port 1 data (negative), USB2.0
USB1_EN_OC#USB Port 1 power enable output and overcurrent input (active low)
USB2_DPUSB Port 2 data (positive) (optional)
USB2_DNUSB Port 2 data (negative) (optional)
USB2_EN_OC#USB Port 2 power enable output and overcurrent input (active low)
(optional)
USB2_SS_TXPUSB Port 2 super speed transmit (positive), USB3.1
USB2_SS_TXNUSB Port 2 super speed transmit (negative), USB3.1
USB2_SS_RXPUSB Port 2 super speed receive (positive), USB3.1
USB2_SS_RXNUSB Port 2 super speed receive (negative), USB3.1
USB3_DPUSB Port 3 data (positive) (optional), USB2.0
USB3_DNUSB Port 3 data (negative) (optional), USB2.0
USB3_EN_OC#USB Port 3 power enable output and overcurrent input (active low)
USB4_DPUSB Port 4 data (positive) (optional), USB2.0
USB4_DNUSB Port 4 data (negative) (optional), USB2.0
USB4_EN_OC#USB Port 4 power enable output and overcurrent input (active low)
(optional)
USB5_DPUSB Port 5 data (positive) (optional), USB2.0
USB5_DNUSB Port 5 data (negative) (optional), USB2.0
USB5_EN_OC#USB Port 5 power enable output and overcurrent input (active low)
(optional)

Speed: High-speed 480Mbit/s Full-speed 12Mbit/s Low-speed 1.5Mbit/s Features: Complies with USB specification rev. 2.0

2.10 Ethernet​

The WILK uses a Realtek RTL8211 integrated 10/100/1000 Mbps Ethernet Transceiver to interface with the GENIO 700 RGMII and a LAN9514 for 10/100 Mbit Ethernet communication.

Table 13: Ethernet pins​

NameDescription
GBE0_MDI0_PETH port 0 differential pair 0 positive signal
GBE0_MDI0_NETH port 0 differential pair 0 negative signal
GBE0_MDI1_PETH port 0 differential pair 1 positive signal
GBE0_MDI1_NETH port 0 differential pair 1 negative signal
GBE0_MDI2_PETH port 0 differential pair 2 positive signal
GBE0_MDI2_NETH port 0 differential pair 2 negative signal
GBE0_MDI3_PETH port 0 differential pair 3 positive signal
GBE0_MDI3_NETH port 0 differential pair 3 negative signal
GBE0_LINK100#ETH port 0 Link Speed indication LED for GBE0 100Mbps (active
low)
GBE0_LINK1000#ETH port 0 Link Speed indication LED for GBE0 1000Mbps (active
low)
GBE0_LINK_ACT#ETH port 0 Link / Activity Indication LED driven Low on Link
(10, 100 or 1000Mbps) Blinks on Activity (active low)
GBE1_MDI0_PETH port 1 differential pair 0 positive signal
GBE1_MDI0_NETH port 1 differential pair 0 negative signal
GBE1_MDI1_PETH port 1 differential pair 1 positive signal
GBE1_MDI1_NETH port 1 differential pair 1 negative signal
GBE1_LINK100#ETH port 1 Link Speed indication LED for GBE0 100Mbps (active
low)
GBE1_LINK_ACT#ETH port 1 Link / Activity Indication LED driven Low on Link
(10, 100 or 1000Mbps) Blinks on Activity (active low)

2.11 CAN​

The WILK uses an MCP2518 SPI to CAN converter.

Table 14: CAN pins​

NameDescription
CAN0_TXCAN 0 transmit data
CAN0_RXCAN 0 receive data

2.12 Display​

2.12.1 LVDS-display​

Table 15: LVDS pins​

NameDescription
LVDS0_TX0_PLVDS port 0 differential pair 0 positive signal
LVDS0_TX0_NLVDS port 0 differential pair 0 negative signal
LVDS0_TX1_PLVDS port 0 differential pair 1 positive signal
LVDS0_TX1_NLVDS port 0 differential pair 1 negative signal
LVDS0_TX2_PLVDS port 0 differential pair 2 positive signal
LVDS0_TX2_NLVDS port 0 differential pair 2 negative signal
LVDS0_TX3_PLVDS port 0 differential pair 3 positive signal
LVDS0_TX3_NLVDS port 0 differential pair 3 negative signal
LVDS0_CK_PLVDS port 0 differential clock pair positive signal
LVDS0_CK_NLVDS port 0 differential clock pair negative signal
LCD0_BKLT_ENBacklight enable signal port 0
LCD0_BKLT_PWMBacklight PWM signal port 0
LCD0_VDD_ENPower control signal port 0

2.12.2 LVDS or eDP (optional)​

Table 16: LVDS or eDP pins​

NameDescription
LVDS1_EDP_D0_PLVDS port 1 differential pair 0 positive signal
or eDP port differential pair 0 positive signal
LVDS1_EDP_D0_NLVDS port 1 differential pair 0 negative signal
or eDP port differential pair 0 negative signal
LVDS1_EDP_D1_PLVDS port 1 differential pair 1 positive signal
or eDP port differential pair 1 positive signal
LVDS1_EDP_D1_NLVDS port 1 differential pair 1 negative signal
or eDP port differential pair 1 negative signal
LVDS1_EDP_D2_PLVDS port 1 differential pair 2 positive signal
or eDP port differential pair 2 positive signal
LVDS1_EDP_D2_NLVDS port 1 differential pair 2 negative signal
or eDP port differential pair 2 negative signal
LVDS1_EDP_D3_PLVDS port 1 differential pair 3 positive signal
or eDP port differential pair 3 positive signal
LVDS1_EDP_D3_NLVDS port 1 differential pair 3 negative signal
or eDP port differential pair 3 negative signal
LVDS1_EDP_CLK_PLVDS port 1 differential clock pair positive signal
or eDP port differential clock pair positive signal
LVDS1_EDP_CLK_NLVDS port 1 differential clock pair negative signal
or eDP port differential clock pair negative signal
LCD1_BKLT_ENBacklight enable signal
LCD1_BKLT_PWMBacklight PWM signal
LCD1_VDD_ENPower control signal

2.12.3 HDMI-display​

Table 17: HDMI pins​

NameDescription
HDMI_D0+HDMI port differential pair 0 positive signal
HDMI_D0-HDMI port differential pair 0 negative signal
HDMI_D1+HDMI port differential pair 0 positive signal
HDMI_D1-HDMI port differential pair 0 negative signal
HDMI_D2+HDMI port differential pair 0 positive signal
HDMI_D2-HDMI port differential pair 0 negative signal
HDMI_CK+HDMI port differential clock positive signal
HDMI_CK-HDMI port differential clock negative signal
HDMI_HPDHDMI Hot Plug Active High Detection Signal
HDMI_CTRL_CKI2C clock line dedicated to HDMI
HDMI_CTRL_DATI2C data line dedicated to HDMI

2.13 Camera​

The GENIO 700 processor got two MIPI CSI camera interfaces. They are connected to the SMARC connector.

Table 17: Camera pins​

NameDescription
CSIO_CK_PCSI port 0 differential clock pair positive signal
CSIO_CK_NCSI port 0 differential clock pair negative signal
CSIO_RX0_PCSI port 0 differential pair 0 positive signal
CSIO_RX0_NCSI port 0 differential pair 0 negative signal
CSIO_RX1_PCSI port 0 differential pair 1 positive signal
CSIO_RX1_NCSI port 0 differential pair 1 negative signal
GPIO0/CAM0_PWR#Camera 0 power enable signal (active low)
GPIO2/CAM0_RST#Camera 0 reset signal (active low)
CSI1_CK_PCSI port 1 differential clock pair positive signal
CSI1_CK_NCSI port 1 differential clock pair negative signal
CSI1_RX0_PCSI port 1 differential pair 0 positive signal
CSI1_RX0_NCSI port 1 differential pair 0 negative signal
CSI1_RX1_PCSI port 1 differential pair 1 positive signal
CSI1_RX1_NCSI port 1 differential pair 1 negative signal
CSI1_RX2_PCSI port 1 differential pair 2 positive signal
CSI1_RX2_NCSI port 1 differential pair 2 negative signal
CSI1_RX3_PCSI port 1 differential pair 3 positive signal
CSI1_RX3_NCSI port 1 differential pair 3 negative signal
GPIO1/CAM1_PWR#Camera 1 power enable signal (active low)
GPIO3/CAM1_RST#Camera 1 reset signal (active low)

Speed:

Features

2.14 Wireless​

The WILK may be equipped with a AzureWave CM276NF WiFi and BT module. The antennas are connected directly to the module.

2.15 PCIe​

The PCIe bus can be used to connect various components.

Table 13: PCIe pins​

NameDescription
REF_CLKP_CARRIERPCIE differential clock pair positive signal
REF_CLKN_CARRIERPCIE differential clock pair negative signal
PCIE_RXP_CARRIERPCIE differential receive positive signal
PCIE_RXN_CARRIERPCIE differential receive negative signal
PCIE_TXP_CARRIERPCIE differential transmit positive signal
PCIE_TXN_CARRIERPCIE differential transmit negative signal
PCIE_A_RST#PCIE reset signal output
PCIE_A_CLKREQ#_CONPCIE A clock request signal input
PCIE_B_CLKREQ#PCIE B clock request signal

3. Specifications

3.1 Absolute Maximum Ratings​

Absolute maximum ratings reflect conditions that the module may be exposed outside of the operating limits, without experiencing immediate functional failure. Functional operation is only expected during the conditions indicated under "Recommended Operating Conditions". Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the module. Exposure to absolute -maximum rated conditions for extended periods may affect device reliability.

| Pin| Min| Max| Unit ---|---|---|---|--- Supply Voltage| 5V_SLEEP| -0.3| 5.5| V | VDD_RTC| -0.3| 3.5| V Storage Temperature| TStorage| -40| +85| °C

| Pin| Min| Typ| Max| Unit ---|---|---|---|---|--- Supply Voltage| 5V_SLEEP| 4.75| 5.0| 5.25| V | VDD_RTC| 2.0| 3.0| 3.25| V Supply current (typ.) Power consumption dramatically depends on the usage scenario. This includes things like if the processors operqaating point (ffrequency) can be set to a lower level; if the GPU can be used by an application; the selected display resolution| @ 5V_SLEEPIdleUsing/RunningTyp. Peak currents when running| | tbdtbdtbd| | mAmAA Operating temperature The chip temperature of processor or LPDDR4 might get hotter. The max. case temperature of 1.MX 93 is specified with xxx (consumer) and xxx (industrial). A higher refresh-rate-setting is needed when case temperature of LPDDR4 is expected to rise above xxx . Temperature of eMMC influence the achievable Data Retention| TConsumerTExtendedTIndustrial| 0-25-40| +25+25+25| +85+85+85| °C°C°C

3.3 ESD Ratings (tbd)​

| | Max| Unit ---|---|---|--- V(ESD) Electrostatic discharge| Human body model (HBM)Charged-device model (CDM)| +/-1000+/-250| VV

3.4 Electrical characteristics​

3.4.1 GENIO 700 GPIO DC parameters. Please view GENIO 700 datasheet for​

details:

| Parameter| Min| Max| Unit ---|---|---|---|--- VIL_1V8| Low-level input voltage| -0.3| 0.35 x VDDIO| V VIH_1V8| High-level input voltage| 0.65 x VDDIO| VDDIO + 0.3| V VOL_1V8| High-level output voltage| | 0.25 x VDDIO| V VOH_1V8| Low-level output voltage| 0.75 x VDDIO| | V RP_up| Pull-Up Resistance| | | kOhm RP_down| Pull-Down Resistance| | | kOhm

3.4.2 STM32 Cortex M0 GPIO DC parameters. Please view STM32 datasheet for​

details:

| Parameter| Min| Max| Unit ---|---|---|---|--- VIL_1V8| Low-level input voltage| -| 0.3 x VDDIO| V VIH_1V8| High-level input voltage| 0.7 x x VDDIO| -| V VOL_1V8| High-level output voltage| -| 0.4| V VOH_1V8| Low-level output voltage| VDDIO - 0.45| -| V RP_up| Pull-Up Resistance| 25 (typ 40)| 55| kOhm RP_down| Pull-Down Resistance| 25 (typ 40)| 55| kOhm

3.5 Mechanical Specification​

Dimensions (mm) of the WILK module (top view)

ToDo: an updated image needs to be inserted