Skip to main content

SOM-Trizeps-VIII-MX8M-Mini ( Trizeps VIII Mini )

Description

The Trizeps VIII Mini is powered by NXP i.MX 8M Mini processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power.

The i.MX 8M Mini family of processors features advanced implementation of a quad ARM® Cortex®-A53 core, which operates at speeds of up to 1.8GHz (consumer version) and 1.5GHz (industrial version). A general purpose Cortex®-M4 core processor is for low-power processing. A 32-bit LPDDR4 is used for memory. There are a number of other i.MX 8M Mini interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

  • a stereo, hi-fi quality audio-codec.

  • a FPGA with up to 4300 LUT to convert parallel display/camera/data-streams to/from MIPI and for user defined programmable logic.

  • a programmable Cortex-M0 for realtime processing, capable of reading multiple 16bit analog inputs, usable as resistive touch-controller and for CAN communication.

  • WLAN 802.11 a/b/g/n/ac and BT 4.2 / 5 module

The Trizeps VIII Mini module got a SODIMM200 card edge connector and a 60pin FX11 high-speed board connector. The pinning of both connectors is to a large extent compatible to previous Trizeps modules. The main difference is the GBit Ethernet feature, which use the pins of the now missing parallel address-/databus.

Difference to Trizeps VIII​

The i.MX8M Mini processor of Trizeps VIII Mini benefits from advanced 14nm LPC FinFET Technology, which allows for lesser power-consumption and higher operating frequencies than the i.MX8 used on Trizeps VIII.

The Trizeps VIII offers more interfaces:

  • HDMI

  • support of 4K displays

  • two USB3.0 instead of USB2.0 ports.

  • additional 4ch MIPI CSI port.

  • larger L2 cache.

The GPIO pinning between both modules is kept the same for maximum compatibility.

Difference to Trizeps VIII Nano​

The i.MX 8M Nano processor of Trizeps VIII Nano is similiar to the i.MX 8M Mini processor used on Trizeps VIII Mini, but has less features.

The Trizeps VIII Nano lacks some interfaces:

  • VPU

  • PCIe

  • only one USB2.0 port.

  • 16bit instead of 32bit LPDDR4.

The GPIO pinning between both modules is kept the same for maximum compatibility. 10 GPIO SODIMM-pins ( 110,112,114,-,130) are not connected on Trizeps VIII Nano.

Block Diagram​

Technical Documents​

Datasheet / Datenblatt: TrizepsVIII- Mini_Datasheet_V3.2

Changes of key components over the revisions​

| Ethernet PHY| LVDS transceiver| Audio Codec ---|---|---|--- V1R1| Qualcomm AR8031| TI SN65DSI8x| Cirrus WM8983 V1R2| Qualcomm AR8031| TI SN65DSI8x| Cirrus WM8983 V1R3| Qualcomm AR8031| TI SN65DSI8x| Cirrus WM8983 V2R1| REALTEK RTL8211| QuickLogic ArcticLink-III-BX6| Cirrus WM8983 V2R2| REALTEK RTL8211| QuickLogic ArcticLink-III-BX6| Cirrus WM8983 V3R1| REALTEK RTL8211| QuickLogic ArcticLink-III-BX6| Cirrus WM8962

Features and Interfaces

Features​

Processor:​

NXP i.MX 8M Mini ARM® Quad Cortex-A53 at up to 1.8GHz (consumer), 1.6GHz (industrial) NXP i.MX 8M Mini ARM® Cortex-M4 NXP Kinetis V ARM® Cortex-M0+ at up to 75MHz

Memory:​

1 or 2 GByte of 32-bit LPDDR4-3200 Higher densities are available on request.

Storage:​

Micro-SD socket or 4 or 8 GByte eMMC Higher densities are available on request.

Wireless:​

WLAN 802.11 a/b/g/n/ac BT 4.2 and BT 5.0 ready Micro RF-antenna connector

Power:​

PMIC to generate all internal and external voltages from 3.3V supply.

Dimensions:​

(Length x Width x Height): 67.6 x 36.7 x 6.4 mm

Interfaces / Signals accessible over connectors​

  • Power Supply through +3.3V.

  • 2x USB2.0 OTG port (USB Host or Slave).

  • PCIe

  • SD/SDIO Card Interface

  • 4x UART

  • SPI and Quad-SPI

  • 2x I2C

  • Mipi Display (4ch) or Single/Dual LVDS or parallel RGB Display.

  • 1x Mipi Camera (4ch).

  • 1Gbit,100/10Mbit Ethernet

  • 1x CAN

  • 2x 4ch 16bit ADC

  • Stereo Headphone

  • Stereo Line-In

  • Microphone input

  • 1W Speaker output

  • SPDIF In and Out

  • Multi-Channel Serial-Audio-Interface

  • GPIO, PWM

1 Pin-description

The main connector of the Trizeps VIII Mini is the SODIMM200 connector. To operate, only +3V3 and GND pins need to be connected. Leave unused pins unconnected. The U14 Board2Board connector can be omitted if the signals are not needed. J1 and J2 may be used for debugging, programming and testing. On the bottom side are UFL antenna connectors for the on-board WLAN + BT chip.

J2: FPGA and MCU JTAG J1: i.MX 8M Mini JTAG

U14: Board2Board Connector

Figure 1-1: Connectors

1.1 Pin-Description (Primary Function)​

The i.MX8M Mini processor, the Cortex M0+ MCU and the FPGA are highly configurable devices, where each pin may have multiple different functions. The pin-names are derived from previous Trizeps-versions and their primary or most interesting function. Please view chapter "1.2 Pin-Mux Information" for details on how these pins may be configured by software.

Notes:

*1) In the table below, some of the old Trizeps pin-names are placed in brackets [ ] for reference.

*2) FPGA_CIF_D[9..0] / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M function is described.

*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M pins, if the FPGA is not mounted (RA3).

*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

J500: SODIMM Connector​

SignalPinPinSignal
AUDIO_MIC_OUT12VIN_AD3 (MCU)
AUDIO_MIC_GND34VIN_AD2 (MCU)
AUDIO_LINEIN_L56VIN_AD1 (MCU)
AUDIO_LINEIN_R78VIN_AD0 (MCU)
AUDIO_AGND910AUDIO_VDDA
AUDIO_AGND1112AUDIO_VDD_SPEAKER
AUDIO_HEADPHONE_GND1314TSPX (MCU)
AUDIO_HEADPHONE_L1516TSMX (MCU)
AUDIO_HEADPHONE_R1718TSPY (MCU)
UART3_RXD1920TSMY (MCU)
UART3_TXD2122SPIN22_RTS3
UART1_DTR2324SPIN24_CTS3
UART1_CTS2526RESET_IN
UART1_RTS2728SPEAKER_R
UART1_DSR2930SPEAKER_L
UART1_DCD3132UART2_CTS
UART1_RXD3334UART2_RTS
UART1_TXD3536UART2_RXD
UART1_RI3738UART2_TXD
GND3940VCC (+3V3)
GND4142VCC (+3V3)
SPIN434344FPGA_LCD_DE
SPIN454546FPGA_LCD_D07
SD2_CLK4748FPGA_LCD_D09
SAI1_RXD04950FPGA_LCD_D11
SD2_DATA35152FPGA_LCD_D12
SAI1_RXD15354FPGA_LCD_D13
SPIN555556FPGA_LCD_PCLK
SAI1_RXD25758FPGA_LCD_D03
SD2_DETECT5960FPGA_LCD_D02
SAI1_RXD36162FPGA_LCD_D08
SAI1_RXD46364FPGA_LCD_D15
SAI1_RXD56566FPGA_LCD_D14
SAI1_RXD66768FPGA_LCD_HSYNC
LED_GPIO6970FPGA_LCD_D01
SAI1_RXD77172FPGA_LCD_D05
SAI5_RXD17374FPGA_LCD_D10
SAI5_RXD27576FPGA_LCD_D00
BACKLIGHT_PWM7778FPGA_LCD_D04
POWERFAIL7980FPGA_LCD_D06
SD2_DATA18182FPGA_LCD_VSYNC
GND8384VCC (+3V3)
SD2_DATA28586FPGA_CIF_VSYNC (*3)
RESET_OUT8788SAI1_MCLK (*3)
+3V3_AUX8990SAI1_RXC (*3)
+3V3_AUX9192SAI1_RXFS (*3)
SPIN93 [RD/WR]9394I2C1_SCL
SPIN95 [RDY]9596I2C1_SDA
CAN1_RX (MCU)9798GPIO_AUX
CAN1_TX (MCU)99100DISPLAY_ENABLE
SPIN101101102AUDIO_ENABLE
SPIN103103104SPIN104
QSPI_SCLK [CS1]105106SAI5_MCLK
QSPI_SS0 [CS3]107108VCC (+3V3)
GND109110SAI1_TXD0 [A08]
QSPI_DATA0 [A00]111112SAI1_TXD1 [A09]
QSPI_DATA1 [A01]113114SAI1_TXD2 [A10]
PCIE_CLKREQ (*5)115116SAI1_TXD3 [A11]
QSPI_DATA2 [A03]117118SAI1_TXD4 [A12]
QSPI_DATA3 [A04]119120SAI1_TXD5 [A13]
SPIN121 [A05]121122SAI1_TXD6 [A14]
CSI1_PWDN [A06]123124SAI1_TXD7 [A15]
CSI1_RESET [A07]125126SAI1_TXFS [DQM0]
USB1_PEN127128SAI1_TXC [DQM1]
USB2_PEN129130-
USB2_OC131132SPIN132
USB1_OC133134SPIN134
USB1_VBUS135136SPIN136
USB1_ID137138-
USB1_DP139140-
USB1_DN141142-
USB2_DP143144-
USB2_DN145146BT_PCM_IN [A19] (*4)
GND147148VCC (+3V3)
-149150FPGA_LCD_D16
-151152FPGA_LCD_D17
-153154PCIE_WAKE
-155156VDD_FPGA_MIPI
-157158PCIE_REFCLK_N
SPDIF_IN [D05]159160PCIE_REFCLK_P
SPDIF_OUT [D06]161162PCIE_TXN_P
SPDIF_EXT_CLK [D07]163164PCIE_TXN_N
-165166PCIE_RXN_P
-167168PCIE_RXN_N
VDD_ENET_IO [D10]169170FPGA_LCD_D21
ETH_LED_SPEED1000 [D11]171172FPGA_LCD_D20
ETH_TRX2_N [D12]173174FPGA_LCD_D19
ETH_TRX2_P [D13]175176FPGA_LCD_D18
ETH_TRX3_N [D14]177178FPGA_LCD_D23
ETH_TRX3_P [D15]179180FPGA_LCD_D22
GND181182VCC (+3V3)
ETH_LED_LINK_AKT183184BT_PCM_OUT (*4)
ETH_LED_SPEED185186BT_PCM_CLK (*4)
ETH_TRX0_N187188BT_PCM_SYNC (*4)
ETH_TRX0_P189190SD2_CMD
ETH_GND191192SD2_DATA0
ETH_TRX1_N193194I2C2_SDA
ETH_TRX1_P195196I2C2_SCL
GND197198VCC (+3V3)
GND199200VCC_SNVS (+3V3)

J400: Board2Board Connector

SignalPinPinSignal
MIPI_CSI1_D2_P12MIPI_DSI_D3_P
MIPI_CSI1_D2_N34MIPI_DSI_D3_N
MIPI_CSI1_D3_P56MIPI_DSI_D2_P
MIPI_CSI1_D3_N78MIPI_DSI_D2_N
-910LVDS1_TX2_P
GND1112GND
-1314LVDS1_TX2_N
-1516LVDS1_TX3_N
-1718LVDS1_TX3_P
-1920LVDS1_CLK_P
-2122LVDS1_CLK_N
-2324LVDS1_TX0_P
-2526LVDS1_TX0_N
-2728LVDS1_TX1_P
-2930LVDS1_TX1_N
MIPI_DSI_D1_P3132MIPI_DSI_D1_N
GND3334GND
LVDS0_TX1_N3536MIPI_DSI_CLK_N
LVDS0_TX1_P3738MIPI_DSI_CLK_P
LVDS0_TX0_P3940-
LVDS0_TX0_N4142-
LVDS0_CLK_N4344-
LVDS0_CLK_P4546-
LVDS0_TX2_P4748-
LVDS0_TX2_N4950-
LVDS0_TX3_P5152-
LVDS0_TX3_N5354-
GND5556GND
MIPI_DSI_D0_N5758-
MIPI_DSI_D0_P5960-
MIPI_CSI1_D0_N6162MIPI_CSI1_CLK_N
MIPI_CSI1_D0_P6364MIPI_CSI1_CLK_P
MIPI_CSI1_D1_P6566MIPI_CSI1_D1_N
GND6768GND

J1: i.MX8M JTAG Connector​

This flex-cable-connector uses the SECO JTAG connector standard. An Adapter to Multi-ICE pin-header is available.

PinSignal
1+3V3_AUX
2GND
3JTAG_TMS
4JTAG_TRST_N
5JTAG_TCK
6JTAG_TDO
7JTAG_TDI
8JTAG_RESET_N

J2: FPGA & MCU JTAG Connector​

This flex-cable-connector uses the SECO JTAG connector standard. An adapter to Multi-ICE pin-header is available.

PinSignal
1VDD_FPGA_MIPI
2GND
3FPGA_JTAG_TMS
4SWD_CLK
5FPGA_JTAG_TCK
6FPGA_JTAG_TDO
7FPGA_JTAG_TDI
8SWD_DIO

1.2 Pin-Mux Information​

Several pins are GPIOs which may be configured for different functions by software. Please check with the processor datasheet for additional pin-mux information. An Excel-Sheet with pin-information is available at:

Notes:

*2) FPGA_CIF_D[9..0] / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M Mini. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M Mini function is described.

*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Mini pins, if the FPGA is not mounted (RA3).

*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

1.2.1 i.MX 8M Mini pins​

The i.MX 8M Mini pins got up to 10 different functions. Only the more common used are listed.

PINNameAlt0Alt1Alt2 / Alt3Alt5
19UART3_RXDecspi1.SCLKuart3.RXgpio5.IO[6]
21UART3_TXDecspi1_MOSIuart3.TXgpio5.IO[7]
22SPIN22_RTS3ecspi1.MISOuart3.CTS_Bgpio5.IO[8]
23UART1_DTRsai5.RX_SYNCsai1.TX_DATA[0]gpio3.IO[19]
24SPIN24_CTS3ecspi1.SS0uart3.RTS_Bgpio5.IO[9]
25UART1_CTSuart3.TXuart1.RTS_Bgpio5.IO[27]
27UART1_RTSuart3.RXuart1.CTS_Bgpio5.IO[26]
29UART1_DSRsai5.RX_BCLKsai1.TX_DATA[1]gpio3.IO[20]
31UART1_DCDsai2.RX_SYNCsai5.TX_SYNCsai5.TX_DATA[1]gpio4.IO[21]
32UART2_CTSuart4.TXuart2.RTS_Bgpio5.IO[29]
33UART1_RXDuart1.RXecspi3.SCLKgpio5.IO[22]
34UART2_RTSuart4.RXuart2.CTS_Bpcie1.CLKREQ_Bgpio5.IO[28]
35UART1_TXDuart1.TXecspi3.MOSIgpio5.IO[23]
36UART2_RXDuart2.RXecspi3.MISOgpio5.IO[24]
37UART1_RIsai2.RX_BCLKsai5.TX_BCLKgpio4.IO[22]
38UART2_TXDuart2.TXecspi3.SS0gpio5.IO[25]
43SPIN43gpio1.IO[7]enet1.MDIOusdhc1.WP
45SPIN45rawnand.CE3_Bqspi.B_SS1_Bgpio3.IO[4]
47SD2_CLKusdhc2.CLKgpio2.IO[13]
49SAI1_RXD0sai1.RX_DATA[0]sai5.RX_DATA[0]sai1.TX_DATA[1]gpio4.IO[2]
51SD2_DATA3usdhc2.DATA3gpio2.IO[18]
53SAI1_RXD1sai1.RX_DATA[1]sai5.RX_DATA[1]gpio4.IO[3]
55SPIN55sai5.RX_DATA[0]sai1.TX_DATA[2]gpio3.IO[21]
57SAI1_RXD2sai1.RX_DATA[2]sai5.RX_DATA[2]gpio4.IO[4]
59SD2_DETusdhc2.CD_Bgpio2.IO[12]
61SAI1_RXD3sai1.RX_DATA[3]sai5.RX_DATA[3]gpio4.IO[5]
63SAI1_RXD4sai1.RX_DATA[4]sai6.TX_BCLKsai6.RX_BCLKgpio4.IO[6]
65SAI1_RXD5sai1.RX_DATA[5]sai6.TX_DATA[0]sai6.RX_DATA[0]sai1.RX_SYNC
gpio4.IO[7]
67SAI1_RXD6sai1.RX_DATA[6]sai6.TX_SYNCsai6.RX_SYNCgpio4.IO[8]
69LED_GPIOsai3.MCLKpwm4.OUTsai5.MCLKgpio5.IO[2]
71SAI1_RXD7sai1.RX_DATA[7]sai6.MCLKsai1.TX_SYNCsai1.TX_DATA[4]
gpio4.IO[9]
73SAI5_RXD1sai5.RX_DATA[1]sai1.TX_DATA[3]sai1.TX_SYNCsai5.TX_SYNC
gpio3.IO[22]
75SAI5_RXD2sai5.RX_DATA[2]sai1.TX_DATA[4]sai1.TX_SYNCsai5.TX_BCLK
gpio3.IO[23]
77BACKLIGHT_PWMgpio1.IO[1]pwm1.OUTanamix.REF_CLK_24M
79POWERFAILsai5.RX_DATA[3]sai1.TX_DATA[5]sai1.TX_SYNCsai5.TX_DATA[0]
gpio3.IO[24]
81SD2_DATA1usdhc2.DATA1gpio2.IO[16]
85SD2_DATA2usdhc2.DATA2gpio2.IO[17]
86FPGA_CIF_VSYNC *3)ecspi2.SS0uart4.RTS_Bgpio5.IO[13]
87RESET_OUTgpio3.IO[14]
88SAI1_MCLKsai1.MCLKsai5.MCLKsai1.TX_BCLKgpio4.IO[20]
90SAI1_RXCsai1.RX_BCLKsai5.RX_BCLKgpio4.IO[1]
92SAI1_RXFSsai1.RX_SYNCsai5.RX_SYNCgpio4.IO[0]
93SPIN93rawnand.WP_Bgpio3.IO[18]
94I2C1_SCLi2c1.SCLenet1.MDCgpio5.IO[14]
95SPIN95rawnand.READY_Bgpio3.IO[16]
96I2C1_SDAi2c1.SDAenet1.MDIOgpio5.IO[15]
98SPIN98gpio1.IO[0]ccmsrcgpcmix.ENET_PHY_REF_CLK_ROOTanamix.REF_CLK_32K
100DISPLAY_ENABLEgpio1.IO[5]m4.NMIccmsrcgpcmix.PMIC_READY
101SPIN101sai3.TX_SYNCgpt1.CAPTURE2sai5.RX_DATA[1]gpio4.IO[31]
102AUDIO_ENABLEgpio1.IO[8]enet1.1588_EVENT0_INusdhc2.RESET_B
103SPIN103sai3.TX_BCLKgpt1.COMPARE2sai5.RX_DATA[2]gpio5.IO[0]
104SPIN104rawnand.DATA05qspi.B_DATA[1]gpio3.IO[11]
105QSPI_SCLKrawnand.ALEqspi.A_SCLKgpio3.IO[0]
106SAI5_MCLKsai5.MCLKsai1.TX_BCLKgpio3.IO[25]
107QSPI_SS0rawnand.CE0_Bqspi.A_SS0_Bgpio3.IO[1]
110SAI1_TXD0sai1.TX_DATA[0]sai5.TX_DATA[0]gpio4.IO[12]
111QSPI_DATA0rawnand.DATA00qspi.A_DATA[0]gpio3.IO[6]
112SAI1_TXD1sai1.TX_DATA[1]sai5.TX_DATA[1]gpio4.IO[13]
113QSPI_DATA1rawnand.DATA01qspi.A_DATA[1]gpio3.IO[7]
114SAI1_TXD2sai1.TX_DATA[2]sai5.TX_DATA[2]gpio4.IO[14]
115PCIE_CLKREQ (*5)i2c4.SCLpwm2.OUTpcie1.CLKREQ_Bgpio5.IO[20]
116SAI1_TXD3sai1.TX_DATA[3]sai5.TX_DATA[3]gpio4.IO[15]
117QPSPI_DATA2rawnand.DATA02qspi.A_DATA[2]gpio3.IO[8]
118SAI1_TXD4sai1.TX_DATA[4]sai6.RX_BCLKsai6.TX_BCLKgpio4.IO[16]
119QSPI_DATA3rawnand.DATA03qspi.A_DATA[3]gpio3.IO[9]
120SAI1_TXD5sai1.TX_DATA[5]sai6.RX_DATA[0]sai6.TX_DATA[0]
gpio4.IO[17]
121SPIN121rawnand.DATA04qspi.B_DATA[0]gpio3.IO[10]
122SAI1_TXD6sai1.TX_DATA[6]sai6.RX_SYNCsai6.TX_SYNCgpio4.IO[18]
123CSI1_PWDNgpio1.IO[3]usdhc1.VSELECTsdma1.EXT_EVENT[0]
124SAI1_TXD7sai1.TX_DATA[7]sai6.MCLKgpio4.IO[19]
125CSI_RESETgpio1.IO[6]enet1.MDCusdhc1.CD_B
126SAI1_TXFSsai1.TX_SYNCsai5.TX_SYNCgpio4.IO[10]
127USB1_PENgpio1.IO[12]usb1.OTG_PWRsdma2.EXT_EVENT[1]
128SAI1_TXCsai1.TX_BCLKsai5.TX_BCLKgpio4.IO[11]
129USB2_PENgpio1.IO[14]usb2.OTG_PWRpwm3.OUT
131USB2_OCgpio1.IO[15]usb2.OTG_OCpwm4.OUT
132SPIN32rawnand.DATA06qspi.B_DATA[2]gpio3.IO[12]
133USB1_OCgpio1.IO[13]usb1.OTG_OCpwm2.OUT
134USB1_PD_INTrawnand.CE2_Bqspi.B_SS0_Bgpio3.IO[3]
136USB1_SS_SELrawnand.RE_Bqspi.B_DQSgpio3.IO[15]
146BT_PCM_IN *4)sai3.TX_DATA[0]gpt1.COMPARE3sai5.RX_DATA[3]
gpio5.IO[1]
154PCIE_WAKErawnand.DATA07qspi.B_DATA[3]gpio3.IO[13]
159SPDIF_INspdif1.INpwm2.OUTgpio5.IO[4]
161SPDIF_OUTspdif1.OUTpwm3.OUTgpio5.IO[3]
163SPDIF_EXT_CLKspdif1.EXT_CLKpwm1.OUTgpio5.IO[5]
184BT_PCM_OUT *4)sai3.RX_DATA[0]gpt1.COMPARE1sai5.RX_DATA[0]
gpio4.IO[30]
186BT_PCM_CLK *4)sai3.RX_BCLKgpt1.CLKsai5.RX_BCLKgpio4.IO[29]
188BT_PCM_SYNC *4)sai3.RX_SYNCgpt1.CAPTURE1sai5.RX_SYNCgpio4.IO[28]
190SD2_CMDusdhc2.CMDgpio2.IO[14]
192SD2_DATA0usdhc2.DATA0gpio2.IO[15]
194I2C2_SDAi2c2.SDAenet1.1588_EVENT1_OUTgpio5.IO[17]
196I2C2_SCLi2c2.SCLenet1.1588_EVENT1_INgpio5.IO[16]

1.2.2 Kinetis MCU pins​

Several pins are GPIOs which may be configured for different functions by software.

Please check with the microcontroller datasheet for additional pin-mux information.

PINNameAlt0Alt1Alt2Alt3Alt4Alt5Alt6Alt7
2VIN_AD3ADC0_SE7
ADC1_SE7
ADC1_DM1PTE19SPI0_SINUART1_
RTSI2C0_
SCLSPI0_
SOUT
4VIN_AD2ADC0_SE6
ADC1_SE1
ADC1_DP1PTE18
LLWI_P20SPI0_SOUTUART1_
CTSI2C0_
SDASPI0_
SIN
6VIN_AD1ADC0_DM1
ADC0_SE5
ADC1_SE5PTE17
LLWI_P19SPI0_SCKUART1_
RXFTM_
CLKIN1LPTMR0
_ALT3
8VIN_AD0ADC0_SE1
ADC0_DP1
ADC1_SE0PTE16SPI0_PCS0UART1_
TXFTM_
CLKIN0FTM_
FLT3
14TSPXADC0_SE8
ADC1_SE8PTB0
LLWU_P5I2C0_SCLFTM1_
CH0FTM1_
QD_PHAUART0_
RX
16TSMXADC0_SE9
ADC1_SE9PTB1I2C0_SDAFTM1_
CH1FTM0_
FLT2EWM_INFTM1_
QD_PHBUART0_
TX
18TSPYADC0_SE11
CMP1_IN0PTC2SPI0_PCS2UART1_
CTSFTM0_
CH1FTM2_
CH1
20TSMYADC1_SE4
CMP1_IN4
DAC0_OUTPTE30FTM0_
CH3FTM_
CLKIN1
24SPIN24_
CTS3PTA4
LLWU_P3FTM0_
CH1FTM4_
FLT0FTM0_
FLT3NMI_b
26RESET_INPTA20RESET
97CAN1_RXPTE25
LLWU_P21CAN
_RXFTM0_
CH1I2C0_
SDAEWM_
IN
99CAN1_TXPTE24CAN0_TXFTM0_
CH0I2C0_
SCLEWM_
OUT

*) Only MKV11 MCU, not usable with MKV10 MCU.

ADC_SE Single-Ended ADC ADC_DM/P Differential ADC LLWU Wakeup-Sources EWM External Watchdog Monitor FTM Flexible Timer Module FTM_CH Output Channel FTM_FLT Fault FTM_QD_PH Quadrature Decoder

1.3 Electrical Pin-Information​

PI:Power InputDO:Digital Output
PO:Power OutputDIO:Digital Input/Output
DDI:Differential Input
AI:Analog InputDDO:Differential Output
AO:Analog OutputDDIO:Differential Input/Output
DI:Digital InputODOpen-Drain Output
PD:Pull-Down(PDp: Pull-Down, Pull-behavior can be changed by software)
PU:Pull-UpPUp: Pull-Up, Pull-behavior can be changed by software

If two "types" are specified, the first value determines the type of primary function.

SODIMM​

PINNameTypeVoltageConnected to
1AUDIO_MIC_OUTAIAudio-Codec
3AUDIO_MIC_GNDAIAudio-Codec
5AUDIO_LINEIN_LAIAudio-Codec
7AUDIO_LINEIN_RAIAudio-Codec
9AUDIO_AGNDAnalog Audio
GroundAudio-Codec and VREF- of Kinetis MCU
11AUDIO_AGND
13AUDIO_HEADPHONE_GNDAIAudio-Codec
15AUDIO_HEADPHONE_LAOAudio-Codec
17AUDIO_HEADPHONE_RAOAudio-Codec
19UART3_RXDDI, DIONVCC_3V3i.MX8M and BT module, if no FPGA (RA600)
21UART3_TXDDO, DIONVCC_3V3
23UART1_DTRDO, DIONVCC_3V3i.MX8M
25UART1_CTSDI, DIONVCC_3V3i.MX8M
27UART1_RTSDO, DIONVCC_3V3i.MX8M
29UART1_DSRDI, DIONVCC_3V3i.MX8M
31UART1_DCDDI, DIONVCC_3V3i.MX8M
33UART1_RXDDI, DIONVCC_3V3i.MX8M
35UART1_TXDDO, DIONVCC_3V3i.MX8M
37UART1_RIDI, DIONVCC_3V3i.MX8M
39GNDGround
41GND
43SPIN43DIONVCC_3V3i.MX8M
45SPIN45DIONVCC_3V3i.MX8M
47SD2_CLKDO, DIONVCC_3V3i.MX8M
49SAI1_RXD0DI, DIONVCC_3V3i.MX8M
51SD2_DATA3DIONVCC_3V3i.MX8M
53i.MX8MDI, DIONVCC_3V3i.MX8M
55SPIN55DIONVCC_3V3i.MX8M
57FPGA_CIF_D2DI, DIONVCC_3V3Fi.MX8M
59SD2_DETDI, DIONVCC_3V3i.MX8M
61FPGA_CIF_D3DI, DIONVCC_3V3i.MX8M
63FPGA_CIF_D4DI, DIONVCC_3V3i.MX8M
65FPGA_CIF_D5DI, DIONVCC_3V3i.MX8M
67FPGA_CIF_D6DI, DIONVCC_3V3i.MX8M
69LED_GPIO, PWM4DO, DIONVCC_3V3i.MX8M
71FPGA_CIF_D7DI, DIONVCC_3V3i.MX8M
73FPGA_CIF_D8DI, DIONVCC_3V3i.MX8M
75FPGA_CIF_D9DI, DIONVCC_3V3i.MX8M
77BACKLIGHT_PWMDO, DIONVCC_3V3i.MX8M
79POWERFAILDI, DIONVCC_3V3i.MX8M
81SD2_DATA1DIONVCC_3V3i.MX8M
83GNDGround
85SD2_DATA2DIONVCC_3V3i.MX8M
87RESET_OUTDONVCC_3V3FPGA + i.MX8M + Kinetis MCU
89+3V3_AUX (NVCC_3V3)PO+3V3NVCC_3V3
91+3V3_AUX (NVCC_3V3)
93SPIN93DIONVCC_3V3i.MX8M
95SPIN95DIONVCC_3V3i.MX8M
97CAN1_RXDI, DIOVCC_SNVSKinetis MCU
99CAN1_TXDO, DIO
101SPIN101DIONVCC_3V3i.MX8M
103SPIN103DIONVCC_3V3i.MX8M
105QSPI_SCLK (CS1)DO, DIONVCC_3V3i.MX8M
107QSPI_SS0 ( CS3)DO, DIONVCC_3V3i.MX8M
109GNDGround
111QSPI_DATA0 (A00)DIONVCC_3V3i.MX8M
113QSPI_DATA1 (A01)DIONVCC_3V3i.MX8M
115PCIE_CLKREQDIONVCC_3V3i.MX8M
117QPSPI_DATA2 (A03)DIONVCC_3V3i.MX8M
119QSPI_DATA3 (A04)DIONVCC_3V3i.MX8M
121SPIN121 (A05)DIONVCC_3V3i.MX8M
123CSI1_PWDNDO, DIONVCC_3V3i.MX8M
125CSI_RESETDO, DIONVCC_3V3i.MX8M
127USB1_PENDO, DIONVCC_3V3i.MX8M
129USB2_PENDO, DIONVCC_3V3i.MX8M
131USB2_OCDI, DIONVCC_3V3i.MX8M
133USB1_OCDI, DIONVCC_3V3i.MX8M
135USB1_VBUSDI (PO)+5Vi.MX8M
137USB1_IDDINVCC_3V3i.MX8M
139USB1_DPDDIONVCC_3V3i.MX8M
141USB1_DNDDIONVCC_3V3i.MX8M
143USB2_DPDDIONVCC_3V3i.MX8M
145USB2_DNDDIONVCC_3V3i.MX8M
147GNDGround
149-
151-
153-
155-
157-
159SPDIF_INDI, DIONVCC_3V3i.MX8M
161SPDIF_OUTDO, DIONVCC_3V3i.MX8M
163SPDIF_EXT_CLKDI, DIONVCC_3V3i.MX8M
165-
167-
169VDD_ENET_IOPOEthernet signal IO voltage
171ETH_LED_SPEED1000ODNVCC_3V3Gbit Ethernet-Phy
173ETH_TRX2_NDDIOVDD_ENET_IOGbit Ethernet-Phy
175ETH_TRX2_PDDIOVDD_ENET_IOGbit Ethernet-Phy
177ETH_TRX3_NDDIOVDD_ENET_IOGbit Ethernet-Phy
179ETH_TRX3_PDDIOVDD_ENET_IOGbit Ethernet-Phy
181GNDGround
183ETH_LED_LINK_AKTODNVCC_3V3Gbit Ethernet-Phy
185ETH_LED_SPEEDODNVCC_3V3Gbit Ethernet-Phy
187ETH_TRX0_NDDIOVDD_ENET_IOGbit Ethernet-Phy
189ETH_TRX0_PDDIOVDD_ENET_IOGbit Ethernet-Phy
191ETH_GNDGround
193ETH_TRX1_NDDIOVDD_ENET_IOGbit Ethernet-Phy
195ETH_TRX1_PDDIOVDD_ENET_IOGbit Ethernet-Phy
197GNDGround
199GND
2VIN_AD3AI, DIOVCC_SNVSKinetis MCU, PTE16: ADC0_SE1
4VIN_AD2AI, DIOVCC_SNVSKinetis MCU, PTE17: ADC0_SE5
6VIN_AD1AI, DIOVCC_SNVSKinetis MCU, PTE18: ADC0_SE6
8VIN_AD0AI, DIOVCC_SNVSKinetis MCU, PTE19: ADC0_SE7
10AUDIO_VDDAPIAUDIO_VDDAudio-Codec and VREF+ of Kinetis MCU
12AUDIO_VDD_SPEAKERPIVDD_SPEAKERAudio-Codec and VREF+
of Kinetis MCU
14TSPXAI, DIOVCC_SNVSKinetis MCU, PTB0: ADC1_SE8
16TSMXAI, DIOVCC_SNVSKinetis MCU, PTB1: ADC1_SE9
18TSPYAI, DIOVCC_SNVSKinetis MCU, PTC2:
ADC0_SE11, CMP1_IN0
20TSMYAI, DIOVCC_SNVSKinetis MCU, PTE30: ADC1_SE4, CMP1_IN4
22SPIN22_RTS3DO, DIONVCC_3V3i.MX8M andBT- module, if no FPGA (RA600)
24SPIN24_CTS3DI, DIONVCC_3V3
VCC_SNVSKinetis MCU,
i.MX8M and
BT-module, if no FPGA
(RA600)
optional ONOFF (R627),
optional BOOT_MODE0 (R628)
26RESET_INDIVCC_SNVSKinetis MCU and Reset-Circuit
28SPEAKER_PAOVDD_SPEAKERAudio-Codec
30SPEAKER_NAO
32UART2_CTSDI, DIONVCC_3V3i.MX8M
34UART2_RTSDO, DIONVCC_3V3i.MX8M
36UART2_RXDDI, DIONVCC_3V3i.MX8M
38UART2_TXDDO, DIONVCC_3V3i.MX8M
40VCCPI+3V3
42VCC
44FPGA_LCD_DEDO, DIONVCC_3V3FPGA
46FPGA_LCD_D07DO, DIONVCC_3V3FPGA
48FPGA_LCD_D09DO, DIONVCC_3V3FPGA
50FPGA_LCD_D11DO, DIONVCC_3V3FPGA
52FPGA_LCD_D12DO, DIONVCC_3V3FPGA
54FPGA_LCD_D13DO, DIONVCC_3V3FPGA
56FPGA_LCD_PCLKDO, DIONVCC_3V3FPGA
58FPGA_LCD_D03DO, DIONVCC_3V3FPGA
60FPGA_LCD_D02DO, DIONVCC_3V3FPGA
62FPGA_LCD_D08DO, DIONVCC_3V3FPGA
64FPGA_LCD_D15DO, DIONVCC_3V3FPGA
66FPGA_LCD_D14DO, DIONVCC_3V3FPGA
68FPGA_LCD_HSYNCDO, DIONVCC_3V3FPGA
70FPGA_LCD_D01DO, DIONVCC_3V3FPGA
72FPGA_LCD_D05DO, DIONVCC_3V3FPGA
74FPGA_LCD_D10DO, DIONVCC_3V3FPGA
76FPGA_LCD_D00DO, DIONVCC_3V3FPGA
78FPGA_LCD_D04DO, DIONVCC_3V3FPGA
80FPGA_LCD_D06DO, DIONVCC_3V3FPGA
82FPGA_LCD_VSYNCDO, DIONVCC_3V3FPGA
84VCCPI+3V3
86FPGA_CIF_VSYNCSPI2_SS0DO, DIONVCC_3V3FPGA, RA3 optional route to
i.MX8M SPI2_SS0
88FPGA_CIF_MCLKSPI2_SCLKDO, DIONVCC_3V3FPGA, RA3 optional route to
i.MX8M SPI2_SCLK
90FPGA_CIF_PCLK
SPI2_MISODO, DIONVCC_3V3FPGA, RA3 optional route to i.MX8 SPI2_MISO
92FPGA_CIF_HSYNC
SPI2_MOSIDO, DIONVCC_3V3FPGA, RA3 optional route to i.MX8 SPI2_MOSI
94I2C1_SCLDO, DIONVCC_3V3i.MX8M
96I2C1_SDADO, DIONVCC_3V3i.MX8M
98SPIN98DIONVCC_3V3i.MX8M
100DISPLAY_ENABLEDO, DIONVCC_3V3i.MX8M
102AUDIO_ENABLEDO, DIONVCC_3V3i.MX8M
104SPIN104DIONVCC_3V3i.MX8M
106SAI5_MCLKDO, DIONVCC_3V3i.MX8M
108VCCPI+3V3
110SAI1_TXD0DO, DIONVCC_3V3i.MX8M
112SAI1_TXD1DO, DIONVCC_3V3i.MX8M
114SAI1_TXD2DO, DIONVCC_3V3i.MX8M
116SAI1_TXD3DO, DIONVCC_3V3i.MX8M
118SAI1_TXD4DO, DIONVCC_3V3i.MX8M
120SAI1_TXD5DO, DIONVCC_3V3i.MX8M
122SAI1_TXD6DO, DIONVCC_3V3i.MX8M
124SAI1_TXD7DO, DIONVCC_3V3i.MX8M
126SAI1_TXFSDO, DIONVCC_3V3i.MX8M
128SAI1_TXCDO, DIONVCC_3V3i.MX8M
130-
132SPIN32DIONVCC_3V3i.MX8M
134USB1_PD_INTDI, DIONVCC_3V3i.MX8M
136USB1_SS_SELDO, DIONVCC_3V3i.MX8M
138-
140-
142-
144-
146BT_PCM_INDI, DIONVCC_3V3i.MX8M and BT-Module
148VCCPI+3V3
150FPGA_LCD_D16DO, DIONVCC_3V3FPGA
152FPGA_LCD_D17DO, DIONVCC_3V3FPGA
154PCIE_WAKEDO, DIONVCC_3V3i.MX8M
156VDD_FPGA_MIPIPO+2V5 (programmable)
158PCIE_REFCLK_NDDONVCC_3V3i.MX8M
160PCIE_REFCLK_PDDONVCC_3V3i.MX8M
162PCIE_TXN_PDDONVCC_3V3i.MX8M
164PCIE_TXN_NDDONVCC_3V3i.MX8M
166PCIE_RXN_PDDINVCC_3V3i.MX8M
168PCIE_RXN_NDDINVCC_3V3i.MX8M
170FPGA_LCD_D21DO, DIONVCC_3V3FPGA
172FPGA_LCD_D20DO, DIONVCC_3V3FPGA
174FPGA_LCD_D19DO, DIONVCC_3V3FPGA
176FPGA_LCD_D18DO, DIONVCC_3V3FPGA
178FPGA_LCD_D23DO, DIONVCC_3V3FPGA
180FPGA_LCD_D22DO, DIONVCC_3V3FPGA
182VCCPI+3V3
184BT_PCM_OUTDO, DIONVCC_3V3i.MX8M and BT-Module
186BT_PCM_CLKDO, DIONVCC_3V3i.MX8M and BT-Module
188BT_PCM_SYNCDO, DIONVCC_3V3i.MX8M and BT-Module
190SD2_CMDDO, DIONVCC_3V3i.MX8M
192SD2_DATA0DIONVCC_3V3i.MX8M
194I2C2_SDADIONVCC_3V3i.MX8M
196I2C2_SCLDIONVCC_3V3i.MX8M
198VCCPI+3V3
200VCC_SNVSPI+3V3 (Must be applied first)

2 Interfaces

This chapter includes a short description of all interfaces of the Trizeps VIII Mini. Please consult the processor datasheet for detailed information.

2.1 Power Supply​

The Trizeps VIII Mini can be supplied by a single +3V3 power-supply. But it is possible to supply parts of the modules separately.

NameDescription
+3V3_SNVS+3V3 power input. This supply powers the Kinetis MCU. The Kinetis
MCU controls reset and power to the i.MX8M processor and may be programmed by
customers.
+3V3Main power input.
+3V3_AUX (NVCC_3V3)+3V3 output.
NVCC_3V3 is the IO-voltage for several peripherals of the i.MX8M Mini.
State of GPIO-pins is undefined until +3V3_AUX is available!
AUDIO_VDD+3V3 power input for audio.
Also used as reference-voltage for ADC of Kinetis MCU.
AUDIO_VDD_SPEAKER+3V3 or +5V power input for audio speaker.
AUDIO_AGNDAnalog GND.
VDD_ENET_IO+2V5 power output. Ethernet signal IO voltage.
VDD_FPGA_MIPI+2V5 power output. Voltage is programmable and supplies the
MIPI IO-banks of the FPGA.

2.2 Control-Signals​

NameDescription
RESET_INNegated reset input. 0: reset device, 1: normal operation.
RESET_OUTNegated reset output. 0: device in reset, 1: normal operation.
SPIN24_CTS3Is connected to the programmable Kinetis MCU.
i.e. may be used to control ONOFF or BOOT_MODE-pin of i.MX8M.

1.1 UART​

The i.MX8M provides 4 Universal Asynchronous Receiver/Transmitter. With a transceiver these signals can be converted to RS232, RS485 or IrDA.

The SODIMM200 standard defines 3 UART ports, but all 4 UARTs are accessible through the SODIMM200 connector if needed.

NameDescription
UART1_TXDUART1 transmit output
UART1_RXDUART1 receive input
UART1_RTSUART1 request to send output
UART1_CTSUART1 clear to send input
UART1_DTRUART1 data terminal ready output;
A GPIO is used to emulate this function.
UART1_DSRUART1 data set ready input;
A GPIO is used to emulate this function.
UART1_DCDUART1 data carrier detect input;
A GPIO is used to emulate this function.
UART1_RIUART1 ring indicator input;
A GPIO is used to emulate this function.
UART2_TXDUART2 transmit output
UART2_RXDUART2 receive input
UART2_RTSUART2 request to send output.
This pin can be configured to be UART4_RXD.
UART2_CTSUART2 clear to send input.
This pin can be configured to be UART4_TXD.
UART3_TXDUART3 transmit output;
This signal is routed through the FPGA.
If Trizeps module is without FPGA, there is a mounting option to either route
UART3 to the SODIMM or to the BT-module.
UART3_RXDUART3 receive input;
This signal is routed through the FPGA.
If Trizeps module is without FPGA, there is a mounting option to either route
UART3 to the SODIMM or to the BT-module.
SPIN22_RTS3UART3 request to send output;
This signal is routed through the FPGA.
If Trizeps module is without FPGA, there is a mounting option to either route
UART3 to the SODIMM or to the BT-module.
The SODIMM200-standard does not specify a RTS-pin for UART3.
SPIN24_CTS3UART3 clear to send input;
This signal is routed through the FPGA.
If Trizeps module is without FPGA, there is a mounting option to either
route UART3 to the SODIMM or to the BT-module.
The SODIMM200-standard does not specify a CTS-pin for UART3.

Baudrate: High-speed TIA/EIA-232-F compatible, up to 1Mbit/s IrDA-compatible, up to 115.2 Kbit/s Data-Bits: 7 or 8 bits (RS232) or 9 bit (RS485) Stop-Bits: 1, 2 Parity: None, Even, Odd Features: Hardware-flow-control (RTS,CTS)

2.4 SPI​

The serial peripheral interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals. The i.MX8M features an Enhanced Configurable SPI (ECSPI). The ECSPI2 is routed to the Kinetis MCU and to the FPGA. The FPGA allows to route these signals to pins, that carried the SPI pins on previous Trizeps SODIMM200 modules. If no FPGA is mounted, there is a mounting option to route these signals to FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK.

NameDescription
SPI2_SS0SPI2 Slave Select
SPI2_SCLKSPI2 Clock
SPI2_MISOSPI2 Master In Slave Out
SPI2_MOSISPI2 Master Out Slave In

Speed: up to 52Mbit/s Features: Master & Slave mode

2.5 QSPI​

The Quad Serial Peripheral Interface (QuadSPI) is a synchronous serial port with up to four bidirectional data lines to interface with external serial flash devices. This interface is not part of the SODIMM200 standard.

NameDescription
QSPI_SS0Quad SPI Slave Select
QSPI_SCLKQuad SPI Clock
QSPI_DATA0Quad SPI Data0
QSPI_DATA1Quad SPI Data1
QSPI_DATA2Quad SPI Data2
QSPI_DATA3Quad SPI Data3

Speed: up to 50MHz Features: Master only.

2.6 I2C​

The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave.

NameDescription
I2C2_SCLPrimary I2C; Clock
I2C2_SDAPrimary I2C; Data
I2C1_SCLSecondary I2C; Clock
I2C1_SDASecondary I2C; Data

Speed: Standard mode, up to 100 kbit/s Fast mode, up to 400 kbit/s

Features: Multimaster operation. I2C Bus Specification Version 2.1

2.7 I2S​

The Inter-IC sound interface provides a synchronous audio interface (SAI) and is used to connect to audio codecs. This interface is not part of the SODIMM200 standard.

NameDescription
SAI1_TXCTransmit Bit Clock
SAI1_TXFSTransmit Frame Sync
SAI1_TXD0Serial transmit data channel 0
SAI1_TXD1Serial transmit data channel 1
SAI1_TXD2Serial transmit data channel 2
SAI1_TXD3Serial transmit data channel 3
SAI1_TXD4Serial transmit data channel 4
SAI1_TXD5Serial transmit data channel 5
SAI1_TXD6Serial transmit data channel 6
SAI1_TXD7Serial transmit data channel 7
SAI1_RXCReceive Bit Clock
SAI1_RXFSReceive Frame Sync
SAI1_MCLKAudio Master Clock
SAI1_RXD0Serial receive data channel 0
SAI1_RXD1Serial receive data channel 1
SAI1_RXD2Serial receive data channel 2
SAI1_RXD3Serial receive data channel 3
SAI1_RXD4Serial receive data channel 4
SAI1_RXD5Serial receive data channel 5
SAI1_RXD6Serial receive data channel 6
SAI1_RXD7Serial receive data channel 7
BT_PCM_CLKBT PCM clock (SAI3_RXC)
Optional connected to BT-module.
BT_PCM_SYNCBT PCM Sync (SAI3_RXFS)
Optional connected to BT-module.
BT_PCM_INBT PCM In (SAI3_TXD)
Optional connected to BT-module.
BT_PCM_OUTBT PCM Out (SAI3_RXD)
Optional connected to BT-module.

2.8 SD-Card​

The SD-Card Interface may be used to connect a SD-Card, eMMC or SDIO-hardware to the Trizeps module.

NameDescription
SD2_CMDSD-card command output
SD2_CLKSD-card clock output
SD2_DAT0SD-card data bit 0
SD2_DAT1SD-card data bit 1
SD2_DAT2SD-card data bit 2
SD2_DAT3SD-card data bit 3
SD2_DETSD-card detect: 1: card inserted, 0: card removed

Speed: Card bus clock frequency up to 208 MHz Features: Conforms to the SD Host Controller Standard Specification version 3.0 Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/5.0

Compatible with the SD Memory Card Spec. vers.. 3.0 and supports the Extended Capacity SD Memory Card Compatible with the SDIO Card Specification version 3.0.

2.9 USB​

The Trizeps VIII Mini got one high-speed USB 2.0 OTG port which may work as host or as slave.

NameDescription
USB1_DPUSB1 Data Plus
USB1_DNUSB1 Data Negative
USB1_PENUSB1 Power Enable output
USB1_OCUSB1 Overcurrent Detect input
USB1_VBUSUSB1 VBUS (+5V)
USB1_IDUSB1 ID Detect
USB2_DPUSB2 Data Plus
USB2_DNUSB2 Data Negative
USB2_PENUSB2 Power Enable output
USB2_OCUSB2 Overcurrent Detect input

Speed: High-speed 480 Mbit/s Full-speed 12 Mbit/s Low-speed 1.5 Mbit/s

Features: Complies with USB specification rev 2.0 (xHCI compatible)

2.10 PCIe​

The i.MX8M Mini features one PCI Express dual mode (DM) controller. The PCIe port is connected to the internal Wireless module. On modules without Wireless the signals are available on the SODIMM200 connector.

NameDescription
PCIE_REFCLK_NPCIE Clock (negative)
PCIE_REFCLK_PPCIE Clock (positive)
PCIE_TXN_NPCIE Transmit Data (negative)
PCIE_TXN_PPCIE Transmit Data (positive)
PCIE_RXN_NPCIE Receive Data (negative)
PCIE_RXN_PPCIE Receive Data (positive)
PCIE_WAKE
PCIE_CLKREQ

Speed: 1.5 / 2.5 / 3.0 / 5.0 / 6.0 Gbps

Features: PCIe specification Gen2 x1 lane PCI Express 1.1/2.0 standard PCI Express Base Specification, Revision 4.0, Version 0.7 PIPE Specification for PCI Express, Version 4.3 PCI Local Bus Specification, Revision 3.0 PCI Bus Power Management Specification, Revision 1.2

2.11 Ethernet​

From V2Rx on Trizeps VIII Mini uses a Realtek RTL8211 integrated 10/100/1000 Mbps Ethernet transceiver to interface with the i.MX8M Mini RGMII. In the older revisions V1Rx an Atheros (Qualcomm) AR8031 was used.

NameDescription
ETH_TRX0_NEthernet Transmit/Receive Data 0 (negative)
ETH_TRX0_PEthernet Transmit/Receive Data 0 (positive)
ETH_TRX1_NEthernet Transmit/Receive Data 1 (negative)
ETH_TRX1_PEthernet Transmit/Receive Data 1 (positive)
ETH_TRX2_NEthernet Transmit/Receive Data 2 (negative)
ETH_TRX2_PEthernet Transmit/Receive Data 2 (positive)
ETH_TRX3_NEthernet Transmit/Receive Data 3 (negative)
ETH_TRX3_PEthernet Transmit/Receive Data 3 (positive)
ETH_LED_LINK_AKTLED output for 10/100/1000 BASE-T activity
ETH_LED_SPEEDLED output for 10 / 100 BASE-T link
ETH_LED_SPEED1000LED output for 1000 BASE-T link
VDD_ENET_IO+2V5 IO-voltage output.

In addition to the normal copper interface, the transceiver incorporates a 1.25GHz SerDes. This interface can be connected directly to a fiber-optic transceiver for 1000 BASE-X / 100 BASE-FX mode or to MAC-device for SGMII interface.

NameDescription
ETH_SI_NSGMII/1000FX Input (negative)
ETH_SI_PSGMII/1000FX Input (positive)
ETH_SO_NSGMII/1000FX Output (negative)
ETH_SO_PSGMII/1000FX Output (positive)

2.12 CAN​

The CAN interface of the Trizeps VIII Mini is implemented through the Kinetis Cortex M0+ MCU.

NameDescription
CAN1_RXCAN1 Receive Data
CAN1_TXCAN1 Transmit Data

2.13 Display​

The i.MX8M processor has this display interfaces:

  • DSI-MIPI (4ch)

The DSI-MIPI interface can be converted to:

  • Single-/Dual-LVDS ( through on board MIPI->LVDS transceiver)

  • parallel RGB Display ( through on board FPGA)

NameDescription
DISPLAY_ENABLEThis GPIO is typical used to control the display-enable signal
of an attached display.
BACKLIGHT_PWMThis GPIO is capable of generating a PWM and is typical used to
generate the backlight PWM signal.

2.13.1 DSI-MIPI (4ch)​

The DSI-MIPI signals are routed to an FPGA, MIPI->LVDS Transceiver and to the B2B-connector.

NameDescription
MIPI_DSI_CLK_PDSI Clock (positive)
MIPI_DSI_CLK_NDSI Clock (negative)
MIPI_DSI_D0_PDSI Data 0 (positive)
MIPI_DSI_D0_NDSI Data 0 (negative)
MIPI_DSI_D1_PDSI Data 1 (positive)
MIPI_DSI_D1_NDSI Data 1 (negative)
(MIPI_DSI_D2_P)
LVDS1_TX1_PDSI Data 2 (positive);
This is a mounting option (RA4), to route this pin to the B2B-connector, when
no LVDS-transceiver is used.
(MIPI_DSI_D2_N)
LVDS1_TX1_NDSI Data 2 (negative);
This is a mounting option (RA4), to route this pin to the B2B-connector, when
no LVDS-transceiver is used.
(MIPI_DSI_D3_P)
LVDS1_TX0_PDSI Data 3 (positive);
This is a mounting option (RA4), to route this pin to the B2B-connector, when
no LVDS-transceiver is used.
(MIPI_DSI_D3_N)
LVDS1_TX0_NDSI Data 3 (negative);
This is a mounting option (RA4), to route this pin to the B2B-connector, when
no LVDS-transceiver is used.

Speed: Support 80Mbps – 1.5Gbps data rate in high speed operation Support 10Mbps data rate in low power operation.

Features: Compliant to MIPI-DSI standard v1.1

2.13.2 Single-/Dual LVDS​

The Trizeps VIII Mini can be equipped with a QuickLogic ArctikLink III (Single- and Dual LVDS) MIPI DSI to LVDS bridge.

In older revisions V1Rx the conversion was done with TI SN65DSI83 (Single- LVDS) or SN65DSI85 (Dual-LVDS) MIPI DSI to LVDS bridge. For SN65DSI83 mounting option, only channel A could be used.

NameDescription
LVDS0_CLK_PChannel A LVDS Clock (positive)
LVDS0_CLK_NChannel A LVDS Clock (negative)
LVDS0_TX0_PChannel A LVDS Data 0 (positive)
LVDS0_TX0_NChannel A LVDS Data 0 (negative)
LVDS0_TX1_PChannel A LVDS Data 1 (positive)
LVDS0_TX1_NChannel A LVDS Data 1 (negative)
LVDS0_TX2_PChannel A LVDS Data 2 (positive)
LVDS0_TX2_NChannel A LVDS Data 2 (negative)
LVDS0_TX3_PChannel A LVDS Data 3 (positive)
LVDS0_TX3_NChannel A LVDS Data 3 (negative)
LVDS1_CLK_PChannel B LVDS Clock (positive)
LVDS1_CLK_NChannel B LVDS Clock (negative)
LVDS1_TX0_PChannel B LVDS Data 0 (positive)
LVDS1_TX0_NChannel B LVDS Data 0 (negative)
LVDS1_TX1_PChannel B LVDS Data 1 (positive)
LVDS1_TX1_NChannel B LVDS Data 1 (negative)
LVDS1_TX2_PChannel B LVDS Data 2 (positive)
LVDS1_TX2_NChannel B LVDS Data 2 (negative)
LVDS1_TX3_PChannel B LVDS Data 3 (positive)
LVDS1_TX3_NChannel B LVDS Data 3 (negative)

2.13.3 Parallel RGB Display​

The Trizeps VIII Mini can be equipped with a Lattice MachXO3 FPGA with up to 4300LUT. This FPGA may be programmed to convert the MIPI-DSI data stream into parallel display output. Although this allows flexible pinning, it is recommended to follow the Trizeps SODIMM200 standard.

NameDescription
FPGA_LCD_PCLKPixel-Clock
FPGA_LCD_DEData-Enable / Data-Valid
FPGA_LCD_HSYNCHorizontal Sync
FPGA_LCD_VSYNCVertical Sync
FPGA_LCD_D00blue [0]
FPGA_LCD_D01blue [1]
FPGA_LCD_D02blue [2]
FPGA_LCD_D03blue [3]
FPGA_LCD_D04blue [4]
FPGA_LCD_D0524bpp: blue [5]
FPGA_LCD_D0624bpp: blue [6]
FPGA_LCD_D0724bpp: blue [7]
FPGA_LCD_D0824bpp: green [0]
FPGA_LCD_D0924bpp: green [1]
FPGA_LCD_D1024bpp: green [2]
FPGA_LCD_D1124bpp: green [3]
FPGA_LCD_D1224bpp: green [4]
FPGA_LCD_D1324bpp: green [5]
FPGA_LCD_D1424bpp: green [6]
FPGA_LCD_D1524bpp: green [7]
FPGA_LCD_D1624bpp: red [0]
FPGA_LCD_D1724bpp: red [1]
FPGA_LCD_D1824bpp: red [2]
FPGA_LCD_D1924bpp: red [3]
FPGA_LCD_D2024bpp: red [4]
FPGA_LCD_D2124bpp: red [5]
FPGA_LCD_D2224bpp: red [6]
FPGA_LCD_D2324bpp: red [7]

2.14 Camera​

The i.MX8M Mini Processor got one MIPI CSI camera interface. It is connected to the B2B-connector.

In earlier versions the second MIPI CSI camera interface (CSI2) was connected to the on-board FPGA and a mounting option existed to connect it to the MIPI CSI1 signals.

NameDescription
MIPI_CSI1_CLK_NMain camera clock input – negative
MIPI_CSI1_CLK_PMain camera clock input – positive
MIPI_CSI1_D0_NMain camera data lane 0 – negative
MIPI_CSI1_D0_PMain camera data lane 0 – positive
MIPI_CSI1_D1_NMain camera data lane 1 – negative
MIPI_CSI1_D1_PMain camera data lane 1 – positive
MIPI_CSI1_D2_NMain camera data lane 2 – negative
MIPI_CSI1_D2_PMain camera data lane 2 – positive
MIPI_CSI1_D3_NMain camera data lane 3 – negative
MIPI_CSI1_D3_PMain camera data lane 3 – positive

Speed: Support 80Mbps – 1.5Gbps data rate in high speed operation Support 10Mbps data rate in low power operation.

Features: up to 4-lane; 1.5 Gbps per lane, Support up to 1080p@60fps video capture.

NameDescription
CSI1_PWDNThis GPIO is typical used to control the Power-Down pin of a
camera.
CSI_RESETThis GPIO is typical used to control the Reset-pin of a camera.

The Trizeps VIII Mini could be equipped with a Lattice MachXO3 FPGA with up to 4300LUT. In earlier versions (up to V1R3), this FPGA could be programmed to convert parallel camera data into a MIPI CSI data stream that could be read by the i.MX8M Mini when the CSI2 to CSI1 mounting option was installed. The FPGA_CIF_xxx pins were additionally connected to the SAI interface of the i.MX8M Mini

2.15 Wireless​

The Trizeps VIII Mini may be equipped with a HD Wireless SPB228, Silex SX- PCEAC2 or AzureWave CM276NF module.

The antennas are connected directly to the module.

2.16 Audio​

NameDescription
AUDIO_MIC_OUTMain Microphone input
AUDIO_MIC_GNDMicrophone ground
AUDIO_LINEIN_LLineIn left channel input
AUDIO_LINEIN_RLineIn right channel input
AUDIO_HEADPHONE_LHeadphone left channel output
AUDIO_HEADPHONE_RHeadphone right channel output
AUDIO_HEADPHONE_GNDHeadphone ground sensing input
SPEAKER_PClass-D speaker amp + output
SPEAKER_NClass-D speaker amp – output
AUDIO_ENABLEThis GPIO is typical used to control the enable pin of an
external audio-amplifier connected to the AUDIO_HEADPHONE pins.

2.17 SPDIF​

The i.MX8M Mini supplies a Sony/Philips Digital Interface (SPDIF) stereo transceiver that allows the processor to receive and transmit digital audio.

NameDescription
SPDIF_INSPDIF input
SPDIF_OUTSPDIF output
SPDIF_EXT_CLKSPDIF clock

3 Specifications

3.1 Absolute Maximum Ratings​

Absolute maximum ratings reflect conditions that the module may be exposed outside of the operating limits, without experiencing immediate functional failure. Functional operation is only expected during the conditions indicated under "Recommended Operating Conditions". Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the module. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

| Pin| Min| | Max| Unit ---|---|---|---|---|--- Supply Voltage| +3V3_SNVS+3V3AUDIO_VDDAVDD_SPEAKER| -0.3 -0.3 -0.3 -0.3| | 3.84.04.5 7.0| VVV V Storage Temperature| TStorage| -40| | +85| °C

| Pin| Min| Typ| Max| Unit ---|---|---|---|---|--- Supply Voltage| +3V3_SNVS+3V3AUDIO_VDDAVDD_SPEAKER| 3.13.12.8 2.8| 3.33.33.3 3.3| 3.43.43.4 5.0| VVV V Supply current (typ.)Power consumption dramatically depends on the usage scenario.This includes things like if the processors operating point (frequency) can be set to a lower level; if the GPU can be used by an application; the selected display-resolution or if the module supplies external peripherals i.e. a speaker or if the PMIC charges a battery. We recommend to use a 2A voltage-regulator to supply the module.| @ 3.3VIdleUsing/Running Typ. Peak Currentswhen running.| | tbdtbdtbd| | mAmAA Operating temperatureThe chip temperature of processor or LPDDR4 might get hotter. The max. case temperature of i.MX 8M Mini is specified with +95°C (consumer) and +105°C (industrial).A higher refresh-rate-setting is needed when case temperature of LPDDR4 is expected to rise above +85°C.Temperature of eMMC influence the achievable Data Retention.| TConsumerTExtended TIndustrial| 0 -25 -40| +25+25 +25| +85+85 +85| °C°C °C

3.3 ESD Ratings​

| | Max| Unit ---|---|---|--- V(ESD) Electrostatic discharge| Human body model (HBM) Charged-device model (CDM)| ±1000 ±250| V V

3.4 Electrical Characteristics​

3.4.1 i.MX 8M Mini GPIO DC parameters. Please view i.MX 8M​

Mini datasheet for details:

| Parameter| Min| Max| Unit ---|---|---|---|--- VIL_3V3| Low-level input voltage| -0.3| 0.3 x VDD| V VIH_3V3| High-level input voltage| 0.7 x VDD| VDD + 0.3| V VOH_3V3| High-level output voltage| 0.8 x VDD| VDD| V VOH_3V3| Low-level output voltage| 0| 0.2 x VDD| V RP_up| Pull-Up Resistance (1)| 18| 72| kΩ RP_down| Pull-Down Resistance (1)| 24| 87| kΩ

  • (1) The i.MX 8M Mini does not support internal pull-up/down for VDD=3.3V.

  • (2) The state of the GPIO-pins is undefined until the PMIC has powered-up and +3V3_AUX is supplied.

3.4.2 FPGA single-Ended DC parameters. Please view FPGA datasheet for​

details:

| Parameter| Min| Max| Unit ---|---|---|---|--- VIL_3V3| Low-level input voltage| -0.3| 0.8| V VIH_3V3| High-level input voltage| 2.0| 3.6| V VOH_3V3| High-level output voltage| VCC–0.2 (IOH=-100µA) VCC-0.4 (IOH=-16mA)| -| V VOH_3V3| Low-level output voltage| -| 0.2 (IOL=100µA) 0.4 (IOL=16mA)| V IPU| Pull-Up Current| -30| -309| µA IPD| Pull-Down Current| 30| 305| µA

3.4.3 Cortex M0+ MCU DC parameters. Please view MCU datasheet for details:​

| Parameter| Min| Max| Unit ---|---|---|---|--- VIL_3V3| Low-level input voltage| -| 0.35 x VCC_SNVS| V VIH_3V3| High-level input voltage| 0.7 x VCC_SNVS| -| V VOH_3V3| High-level output voltage| VCC–0.5 (IOH=-5mA) VCC-0.5 (IOH=-18mA)| -| V VOH_3V3| Low-level output voltage| -| 0.5 (IOL=5mA) 0.5 (IOL=18mA)| V IOHT| Output high current total for all ports| -| 100| mA IOLT| Output low current total for all ports| -| 100| mA RPU| Internal pullup resistor| 20| 50| kΩ

3.5 Mechanical Specification​

Dimensions (mm) of the Trizeps VIII Mini module (top view)

Dimensions (mm) of the Trizeps VIII Mini module (bottom view)

4 Article numbers for Trizeps VIII Mini

Current part number definition and examples of standard moduls:

Trizeps VIII mini Partnumber definition 2-2024

History:

Part number definition 1/2024

Part number structure (till end of 2023)

5 Important Notice

6 Document History

Rev.DateAuthorChanges
0.917.04.2019VoBInitial version
1.023.05.2019SHAdded graphics. Corrected some parts.
1.116.10.2019SHUpdated "4.0 Ordercodes for Trizeps VIII Mini"Updated
Temperature and ESD specification.Added remark about i.MX 8M Mini not
supporting internal pull-up/down for 3.3V IO-Voltage.Changed RESET_OUT:
gpio1.IO[2] to gpio3.IO[14] ( V1R1L1 - V1R2L1)
1.223.10.2019SHAdded comment PCIE_CLKREQ signal (SODIMM 115) may not be
used when Wifi-module is mounted. V1R1 - V1R2 change of PCIE_CLKREQ pin form
GPIO5_21 to GPIO5_20.
1.318.11.2019SHCorrected Feature list that i.MX 8M Mini is used.
1.411.12.2019TW/CTUpdated "4.0 Article numbers for Trizeps VIII
Mini".Layout modifications
1.506.04.2019SHAdded info to available Excel-Sheet andGPIO-behaviour
during startup.
1.606.07.2020TWChanged WiFi Connector from UFL to µRF.
1.715.10.2020SHFix wrong reference (changed RA438 to RA3)
1.830.10.2020SHChapter 2.12.2; Fix description:(MIPI_DSI_D3_N) is "DSI
Data 3 (negative)"
2.021.11.2022Update new CI
3.008.05.2023VoBRefers to hardware revision V2 and V3
Major changes:

  • J400 B2B connector assignment

  • J500 SODIMM connector assignment

3.1| 17.05.2024| MS| Part number definition changed to 4GW version 3.1| 29.10.2024| MS| Part number definition changed to SF-59…. Version

SECO Northern Europe GmbH

Schlachthofstraße 20 21079 Hamburg

E-Mail: north@seco.com

All rights reserved. Products subject to technical changes, improvements and misprints. © 2022 SECO Northern Europe GmbH

Software​

Baseboard & Panels​

The Trizeps VIII fits into following Seco products: