Skip to main content

SOM-Trizeps-VIII-MX8M-Plus ( Trizeps VIII Plus )

Description

The Trizeps VIII Plus is powered by NXP i.MX 8M Plus processor, which is designed to meet the latest market requirements of connected streaming audio/video devices, scanning/imaging devices and various devices demanding high-performance and low-power. It offers a 2.3 TOP/s Neural Processing Unit (NPU) for AI-applications like pattern, object and speech recognition.

The i.MX 8M Plus family of processors features advanced implementation of a quad ARM® Cortex®-A53 core, which operates at speeds of up to 1.8GHz (consumer version) and 1.6GHz (industrial version). A general purpose Cortex®-M7 core processor is for low-power processing. A 32-bit LPDDR4 is used for memory. There are a number of other i.MX 8M Plus interfaces for connecting peripherals, such as displays, cameras, GPS and sensors, which are extended by components already available on the module:

  • a stereo, hi-fi quality audio-codec.

  • a FPGA with up to 4300 LUT to convert MIPI-DSI to parallel 24bpp display data and for user defined programmable logic.

  • a programmable Cortex-M0 Kinetis MCU, capable of realtime processing, reading multiple 16bit analog inputs or usable as resistive touch-controller.

  • WLAN 802.11 a/b/g/n/ac and BT 4.2 / 5 module

The Trizeps VIII Plus module got a SODIMM200 card edge connector and a 60pin FX11 high-speed board connector. The pinning of both connectors is to a large extent compatible to previous Trizeps modules.

Difference to Trizeps VIII​

The i.MX 8M Plus processor of Trizeps VIII Plus benefits from advanced 14nm LPC FinFET Technology, which allows for lesser power-consumption and higher operating frequencies than the i.MX8 used on Trizeps VIII.

The Trizeps VIII offers:

  • support of 4K displays

It misses following features:

  • 2.3 TOP/s NPU (Neural Processing Unit)

  • 2x CAN

  • second Ethernet-MAC

  • third SDIO-port routed to SODIMM

Difference to Trizeps VIII Mini​

The i.MX 8M Mini processor of Trizeps VIII Mini can be considered as the predecessor to the i.MX 8M Plus processor used on Trizeps VIII Plus.

The Trizeps VIII Mini lacks some of the interfaces:

  • 2.3 TOP/s NPU (Neural Processing Unit)

  • 2x CAN

  • second Ethernet-MAC

  • third SDIO-port routed to SODIMM

  • HDMI

  • multi-display support: only MIPI-DSI or LVDS may be used at the same time.

  • only USB2.0, instead of USB3.0 ports.

Block Diagram​

Technical Documents​

Manual:

Changes of key components over the revisions​

Ethernet PHYAudio Codec
V1R1Qualcomm AR8031
V1R2Qualcomm AR8031
V1R3REALTEK RTL8211
V1R4REALTEK RTL8211

Features and Interfaces

Features​

Processor:​

NXP i.MX 8M Plus ARM® Quad Cortex-A53 at up to 1.8GHz (consumer), 1.6GHz (industrial) NXP i.MX 8M Plus ARM® Cortex-M7 at up to 800MHz Neural Processing Unit 2.3 TOPS NXP Kinetis V ARM® Cortex-M0+ at up to 75MHz

Memory:​

Up to 8 GByte of 32-bit LPDDR4-4000

Storage:​

Micro-SD socket or 4 or 8 GByte eMMC Higher densities are available on request.

Wireless:​

WLAN 802.11 a/b/g/n/ac BT 4.2 and BT 5.0 Micro RF-antenna connector

Power:​

PMIC to generate all internal and external voltages from VSYS supply.

Dimensions:​

(Length x Width x Height): 67.6 x 36.7 x 6.4 mm

Interfaces / Signals accessible over connectors​

  • Power Supply from +3.3V to +5V

  • 2x USB3.0 OTG port (USB Host or Slave)

  • PCIe

  • 2x SD/SDIO Card Interface

  • 4x UART

  • SPI and Quad-SPI

  • 2x I2C

  • MIPI Display (4ch) or parallel RGB Display

  • Single/Dual LVDS

  • HDMI

  • 2x Mipi Camera (4ch)

  • 1000/100/10Mbit Ethernet

  • 2x CAN/CAN-FD

  • 2x 4ch 16bit ADC

  • Stereo Headphone

  • Stereo Line-In

  • Microphone input (mono, optional stereo)

  • 1W Speaker output

  • SPDIF In and Out

  • Multi-Channel Serial-Audio-Interface

  • GPIO, PWM

1 Pin-description

The main connector of the Trizeps VIII Plus is the SODIMM200 connector. To operate, only VSYS and GND pins need to be connected. Leave unused pins unconnected. The U14 Board2Board connector can be omitted if the signals are not needed. J1 and J2 may be used for debugging, programming and testing. On the bottom side are UFL antenna connectors for the on-board WLAN + BT- chip.

1.1 Pin-description (Primary Function)​

The i.MX8M Plus processor, the Cortex M0+ MCU and the FPGA are highly configurable devices, where each pin may have multiple different functions. The pin-names are derived from previous Trizeps-versions and their primary or most interesting function. Please view chapter "1.2 Pin-Mux Information" for details on how these pins may be configured by software.

Notes:

*1) In the table below, some of the old Trizeps pin-names are placed in brackets [] for reference.

*2) FPGA_CIF_D[9..0] / SAIx_RXD[7..0], FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are routed to the FPGA and the i.MX 8M Plus. In the following documentation they are either named FPGA_CIF_Dx or SAIx_RXDy, depending if the FPGA or i.MX 8M Plus function is described.

*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Plus pins, if the FPGA is not mounted (RA72).

*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

J1: SODIMM Connector​

SignalPinPinSignal
AUDIO_MIC_OUT12VIN_AD3 (MCU)
AUDIO_MIC_GND34VIN_AD2 (MCU)
AUDIO_LINEIN_L56VIN_AD1 (MCU)
AUDIO_LINEIN_R78VIN_AD0 (MCU)
AUDIO_AGND910AUDIO_VDDA
AUDIO_AGND1112AUDIO_VDD_SPEAKER
AUDIO_HEADPHONE_GND1314TSPX (MCU)
AUDIO_HEADPHONE_L1516TSMX (MCU)
AUDIO_HEADPHONE_R1718TSPY (MCU)
UART3_RXD1920TSMY (MCU)
UART3_TXD2122SPIN22_RTS3
UART1_DTR2324SPIN24_CTS3
UART1_CTS2526RESET_IN
UART1_RTS2728SPEAKER_R
UART1_DSR2930SPEAKER_L
UART1_DCD3132UART2_CTS
UART1_RXD3334UART2_RTS
UART1_TXD3536UART2_RXD
UART1_RI3738UART2_TXD
GND3940VSYS (+3V3/+5V)
GND4142VSYS (+3V3/+5V)
SPIN434344LCD_EN
SPIN454546LCD_D07
SD2_CLK4748LCD_D09
CIF_D04950LCD_D11
SD2_DATA35152LCD_D12
CIF_D15354LCD_D13
SPIN555556LCD_PCLK
SAI1_RXD25758LCD_D03
SD2_DETECT5960LCD_D02
SAI1_RXD36162LCD_D08
SAI1_RXD46364LCD_D15
SAI1_RXD56566LCD_D14
SAI1_RXD66768LCD_HSYNC
LED_GPIO6970LCD_D01
SAI1_RXD77172LCD_D05
CIF_D87374LCD_D10
CIF_D97576LCD_D00
BACKLIGHT_PWM7778LCD_D04
POWERFAIL7980LCD_D06
SD2_DATA18182LCD_VSYNC
GND8384VSYS (+3V3/+5V)
SD2_DATA28586CIF_VSYNC (*3)
RESET_OUT8788CIF_MCLK (*3)
+3V3_AUX8990CIF_PCLK (*3)
+3V3_AUX9192CIF_HSYNC (*3)
N.C.9394I2C1_SCL
SPIN95 [RDY]9596I2C1_SDA
CAN1_RX9798GPIO_AUX
CAN1_TX99100DISPLAY_ENABLE
CAN2_RX101102AUDIO_ENABLE
CAN2_TX103104SPIN104
QSPI_SCLK [CS1]105106VSD_3V3
QSPI_SS0 [CS3]107108VSYS (+3V3/+5V)
GND109110SAI1_TXD0
QSPI_DATA0 [A00]111112SAI1_TXD1
QSPI_DATA1 [A01]113114SAI1_TXD2
PCIE_CLKREQ (*5)115116SAI1_TXD3
QSPI_DATA2 [A03]117118SAI1_TXD4
QSPI_DATA3 [A04]119120SAI1_TXD5
SPIN121 [A05]121122SAI1_TXD6
CSI1_PWDN [A06]123124SAI1_TXD7
CSI1_RESET [A07]125126SAI1_TXFS
USB1_PEN127128SAI1_TXC
USB2_PEN129130HDMI_DDC_SCL
USB2_OC131132N.C.
USB1_OC133134SPIN134
USB1_VBUS135136SPIN136
USB1_ID137138USB1_RXP
USB1_DP139140USB1_RXN
USB1_DN141142USB1_TXP
USB2_DP143144USB1_TXN
USB2_DN145146BT_PCM_IN (*4)
GND147148VSYS (+3V3/+5V)
HDMI_DDC_SDA149150LCD_D16
USB2_TXP151152LCD_D17
USB2_TXN153154PCIE_WAKE
USB2_RXP155156VDD_FPGA_MIPI
USB2_RXN157158PCIE_CLK_N
SPDIF_IN [D05]159160PCIE_CLK_P
SPDIF_OUT [D06]161162PCIE_TX_P
SPDIF_EXT_CLK [D07]163164PCIE_TX_N
LED_WL165166PCIE_RX_P
LED_BT [D09]167168PCIE_RX_N
VDD_ENET_IO [D10]169170FPGA_LCD_D21 or SD3_DATA0
ETH_LED_SPEED1000 [D11]171172FPGA_LCD_D20 or SD3_DATA1
ETH_TRX2_N [D12]173174FPGA_LCD_D19 or SD3_DATA2
ETH_TRX2_P [D13]175176FPGA_LCD_D18 or SD3_DATA3
ETH_TRX3_N [D14]177178FPGA_LCD_D23 or SD3_CLK
ETH_TRX3_P [D15]179180FPGA_LCD_D22 or SD3_CMD
GND181182VSYS (+3V3/+5V)
ETH_LED_LINK_AKT183184BT_PCM_OUT (*4)
ETH_LED_SPEED100185186BT_PCM_CLK (*4)
ETH_TRX0_N187188BT_PCM_SYNC (*4)
ETH_TRX0_P189190SD2_CMD
ETH_GND191192SD2_DATA0
ETH_TRX1_N193194I2C2_SDA
ETH_TRX1_P195196I2C2_SCL
GND197198VSYS (+3V3/+5V)
GND199200VCC_SNVS (+3V3)

J2: Board2Board Connector​

SignalPinPinSignal
MIPI_CSI1_D2_P12MIPI_DSI_D3_P
MIPI_CSI1_D2_N34MIPI_DSI_D3_N
MIPI_CSI1_D3_P56MIPI_DSI_D2_P
MIPI_CSI1_D3_N78MIPI_DSI_D2_N
MIPI_CSI2_CLK_P910LVDS1_TX2_P
GND1112GND
MIPI_CSI2_CLK_N1314LVDS1_TX2_N
MIPI_CSI2_D0_P1516LVDS1_TX3_N
MIPI_CSI2_D0_N1718LVDS1_TX3_P
MIPI_CSI2_D1_P1920LVDS1_CLK_P
MIPI_CSI2_D1_N2122LVDS1_CLK_N
MIPI_CSI2_D2_P2324LVDS1_TX0_P
MIPI_CSI2_D2_N2526LVDS1_TX0_N
MIPI_CSI2_D3_P2728LVDS1_TX1_P
MIPI_CSI2_D3_N2930LVDS1_TX1_N
MIPI_DSI_D1_P3132MIPI_DSI_D1_N
GND3334GND
LVDS0_TX1_N3536MIPI_DSI_CLK_N
LVDS0_TX1_P3738MIPI_DSI_CLK_P
LVDS0_TX0_P3940HDMI_TX1_P
LVDS0_TX0_N4142HDMI_TX1_N
LVDS0_CLK_N4344HDMI_TX2_P
LVDS0_CLK_P4546HDMI_TX2_N
LVDS0_TX2_P4748HDMI_HPD
LVDS0_TX2_N4950HDMI_CLK_N
LVDS0_TX3_P5152HDMI_CLK_P
LVDS0_TX3_N5354HDMI_CEC
GND5556GND
MIPI_DSI_D0_N5758HDMI_TX0_N
MIPI_DSI_D0_P5960HDMI_TX0_P
MIPI_CSI1_D0_N6162MIPI_CSI1_CLK_N
MIPI_CSI1_D0_P6364MIPI_CSI1_CLK_P
MIPI_CSI1_D1_P6566MIPI_CSI1_D1_N
GND6768GND

J90: i.MX8M JTAG Connector​

This flex-cable-connector uses the SECO Northern Europe JTAG connector standard. An Adapter to Multi-ICE pin-header is available.

PinSignal
1+3V3
2GND
3JTAG_TMS
4N.C.
5JTAG_TCK
6JTAG_TDO
7JTAG_TDI
8JTAG_RESET_N

J91: FPGA & MCU JTAG Connector​

This flex-cable-connector uses the SECO Northern Europe JTAG connector standard. An adapter to Multi-ICE pin-header is available.

PinSignal
1VDD_FPGA_MIPI
2GND
3FPGA_JTAG_TMS
4SWD_CLK
5FPGA_JTAG_TCK
6FPGA_JTAG_TDO
7FPGA_JTAG_TDI
8SWD_DIO

1.2 Pin-Mux Information​

Several pins are GPIOs which may be configured for different functions by software. Please check with the processor datasheet for additional pin-mux information. An Excel-Sheet with pin-information is available at:

Notes:

*3) FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK are connected to i.MX 8M Plus pins, if the FPGA is not mounted (RA72).

*4) BT_PCM_IN, BT_PCM_OUT, BT_PCM_SYNC and BT_PCM_CLK are connected to the on-board BT-module if it is mounted!

*5) PCIE_CLKREQ may not be usable when Wifi module is mounted.

1.2.1 i.MX 8M Plus pins​

The i.MX 8M Plus pins got up to 10 different functions. Only the more common used are listed.

PINNameAlt0Alt1Alt2 / Alt3Alt5
19UART3_RXDecspi1.SCLKuart3.RXgpio5.IO[6]
21UART3_TXDecspi1_MOSIuart3.TXgpio5.IO[7]
22SPIN22_RTS3ecspi1.MISOuart3.CTS_Bgpio5.IO[8]
23UART1_DTRsai5.RX_SYNCsai1.TX_DATA[0]gpio3.IO[19]
24SPIN24_CTS3ecspi1.SS0uart3.RTS_Bgpio5.IO[9]
25UART1_CTSuart3.TXuart1.RTS_Bgpio5.IO[27]
27UART1_RTSuart3.RXuart1.CTS_Bgpio5.IO[26]
29UART1_DSRsai5.RX_BCLKsai1.TX_DATA[1]gpio3.IO[20]
31UART1_DCDsai2.RX_SYNCsai5.TX_SYNCsai5.TX_DATA[1]gpio4.IO[21]
32UART2_CTSuart4.TXuart2.RTS_Bgpio5.IO[29]
33UART1_RXDuart1.RXecspi3.SCLKgpio5.IO[22]
34UART2_RTSuart4.RXuart2.CTS_Bpcie1.CLKREQ_Bgpio5.IO[28]
35UART1_TXDuart1.TXecspi3.MOSIgpio5.IO[23]
36UART2_RXDuart2.RXecspi3.MISOgpio5.IO[24]
37UART1_RIsai2.RX_BCLKsai5.TX_BCLKgpio4.IO[22]
38UART2_TXDuart2.TXecspi3.SS0gpio5.IO[25]
43SPIN43gpio1.IO[7]usdhc1.WP
45SPIN45rawnand.CE3_Bqspi.B_SS1_Bgpio3.IO[4]
47SD2_CLKusdhc2.CLKgpio2.IO[13]
49SAI1_RXD0sai1.RX_DATA[0]sai5.RX_DATA[0]sai1.TX_DATA[1]gpio4.IO[2]
51SD2_DATA3usdhc2.DATA3gpio2.IO[18]
53SAI1_RXD1sai1.RX_DATA[1]sai5.RX_DATA[1]gpio4.IO[3]
55SPIN55sai5.RX_DATA[0]sai1.TX_DATA[2]gpio3.IO[21]
57SAI1_RXD2sai1.RX_DATA[2]sai5.RX_DATA[2]enet1_MDCgpio4.IO[4]
59SD2_DETusdhc2.CD_Bgpio2.IO[12]
61SAI1_RXD3sai1.RX_DATA[3]sai5.RX_DATA[3]enet1_MDIOgpio4.IO[5]
63SAI1_RXD4sai1.RX_DATA[4]sai6.TX_BCLKenet1_RD0gpio4.IO[6]
65SAI1_RXD5sai1.RX_DATA[5]sai6.TX_DATA[0]sai1.RX_SYNC, enet1_RD1gpio4.IO[7]
67SAI1_RXD6sai1.RX_DATA[6]sai6.TX_SYNCsai6.RX_SYNC, enet1_RD2gpio4.IO[8]
69LED_GPIOsai3.MCLKpwm4.OUTsai5.MCLKgpio5.IO[2]
71SAI1_RXD7sai1.RX_DATA[7]sai6.MCLKsai1.TX_SYNC, sai1.TX_DATA[4], enet1_RD3gpio4.IO[9]
73SAI5_RXD1sai5.RX_DATA[1]sai1.TX_DATA[3]sai1.TX_SYNC, sai5.TX_SYNCgpio3.IO[22]
75SAI5_RXD2sai5.RX_DATA[2]sai1.TX_DATA[4]sai1.TX_SYNC, sai5.TX_BCLKgpio3.IO[23]
77BACKLIGHT_PWMgpio1.IO[1]pwm1.OUTanamix.REF_CLK_24M
79SPIN79sai5.RX_DATA[3]sai1.TX_DATA[5]sai1.TX_SYNC, sai5.TX_DATA[0]gpio3.IO[24]
81SD2_DATA1usdhc2.DATA1gpio2.IO[16]
85SD2_DATA2usdhc2.DATA2gpio2.IO[17]
86CIF_VSYNCecspi2.SS0uart4.RTS_Bgpio5.IO[13]
87RESET_OUTgpio3.IO[14]
88SAI1_MCLK/CIF_MCLKsai1.MCLK, ecspi2.SCLKsai5.MCLK, uart4.RXsai1.TX_BCLKgpio4.IO[20], gpio5.IO[10]
90SAI1_RXC/CIF_PCLKsai1.RX_BCLK, ecspi2.MISOsai5.RX_BCLK, uart4.CTS_Bgpio4.IO[1], gpio5.IO[12]
92SAI1_RXFSC/CIF_HSYNCsai1.RX_SYNC, ecspi2.MOSIsai5.RX_SYNC, uart4.TXgpio4.IO[0], gpio5.IO[11]

1.2.2 Kinetis MCU pins​

Several pins are GPIOs which may be configured for different functions by software. Please check with the microcontroller datasheet for additional pin-mux information.

PINNameAlt0Alt1Alt2Alt3Alt4Alt5Alt6Alt7
2VIN_AD3ADC0_SE7, ADC1_SE7, ADC1_DM1PTE19SPI0_SINUART1_RTSI2C0_SCLSPI0_SOUT
4VIN_AD2ADC0_SE6, ADC1_SE1, ADC1_DP1PTE18, LLWI_P20SPI0_SOUTUART1_CTSI2C0_SDASPI0_SIN
6VIN_AD1ADC0_DM, ADC0_SE5, ADC1_SE5PTE17, LLWI_P19SPI0_SCKUART1_RXFTM_CLKIN1LPTMR0_ALT3
8VIN_AD0ADC0_SE1, ADC0_DP, ADC1_SE0PTE16SPI0_PCS0UART1_TXFTM_CLKIN0FTM_FLT3
14TSPXADC0_SE8, ADC1_SE8PTB0, LLWU_P5I2C0_SCLFTM1_CH0FTM1_QD_PHAUART0_RX
16TSMXADC0_SE9, ADC1_SE9PTB1I2C0_SDAFTM1_CH1FTM0_FLT2EWM_INFTM1_QD_PHBUART0_TX
18TSPYADC0_SE11, CMP1_IN0PTC2SPI0_PCS2UART1_CTSFTM0_CH1FTM2_CH1
20TSMYADC1_SE4, CMP1_IN4, DAC0_OUTPTE30FTM0_CH3FTM_CLKIN1
24SPIN24_CTS3PTA4, LLWU_P3FTM0_CH1FTM4_FLT0FTM0_FLT3NMI_b
26RESET_INPTA20RESET
97CAN1_RXPTE25, LLWU_P21CAN0_RXFTM0_CH1I2C0_SDAEWM_IN
99CAN1_TXPTE24CAN0_TXFTM0_CH0I2C0_SCLEWM_OUT

*) Only MKV11 MCU, not usable with MKV10 MCU.

ADC_SE Single-Ended ADC ADC_DM/P Differential ADC LLWU Wakeup-Sources EWM External Watchdog Monitor FTM Flexible Timer Module FTM_CH Output Channel FTM_FLT Fault FTM_QD_PH Quadrature Decoder

1.3 Electrical Pin-Information​

AbbreviationMeaning / Description
PIPower Input
POPower Output
AIAnalog Input
AOAnalog Output
DIDigital Input
DODigital Output
DIODigital Input/Output
DDIDifferential Input
DDODifferential Output
DDIODifferential Input/Output
ODOpen-Drain Output
PDPull-Down (PDp: Pull-Down, pull behavior can be changed by software)
PUPull-Up (PUp: Pull-Up, pull behavior can be changed by software)

If two "types" are specified, the first value determines the type of primary

SODIMM​

PINNameTypeVoltageConnected to
1AUDIO_MIC_OUTAIAudio-Codec
3AUDIO_MIC_GNDAIAudio-Codec
5AUDIO_LINEIN_LAIAudio-Codec
7AUDIO_LINEIN_RAIAudio-Codec
9AUDIO_AGNDAnalogAudio-Codec and VREF- of Kinetis MCU
11AUDIO_AGNDAnalogAudio-Codec and VREF- of Kinetis MCU
13AUDIO_HEADPHONE_GNDAIAudio-Codec
15AUDIO_HEADPHONE_LAOAudio-Codec
17AUDIO_HEADPHONE_RAOAudio-Codec
19UART3_RXDDI, DIONVCC_3V3i.MX8M and BT-module, if no FPGA (RA600)
21UART3_TXDDO, DIONVCC_3V3SPI1_CLK
23UART1_DTRDO, DIONVCC_3V3i.MX8M
25UART1_CTSDI, DIONVCC_3V3i.MX8M
27UART1_RTSDO, DIONVCC_3V3i.MX8M
29UART1_DSRDI, DIONVCC_3V3i.MX8M
31UART1_DCDDI, DIONVCC_3V3i.MX8M
33UART1_RXDDI, DIONVCC_3V3i.MX8M
35UART1_TXDDO, DIONVCC_3V3i.MX8M
37UART1_RIDI, DIONVCC_3V3i.MX8M
39GNDGround
41GNDGround
43SPIN43DIONVCC_3V3i.MX8M
45SPIN45DIONVCC_3V3i.MX8M
47SD2_CLKDO, DIONVCC_3V3i.MX8M
49CIF_D0DI, DIONVCC_3V3i.MX8M
51SD2_DATA3DIONVCC_3V3i.MX8M
53CIF_D1DI, DIONVCC_3V3i.MX8M
55SPIN55DIONVCC_3V3i.MX8M
57SAI1_RXD2DI, DIONVCC_3V3i.MX8M
59SD2_DETDI, DIONVCC_3V3i.MX8M
61SAI1_RXD3DI, DIONVCC_3V3i.MX8M
63SAI1_RXD4DI, DIONVCC_3V3i.MX8M
65SAI1_RXD5DI, DIONVCC_3V3i.MX8M
67SAI1_RXD6DI, DIONVCC_3V3i.MX8M
69LED_GPIO, PWM4DO, DIONVCC_3V3i.MX8M
71SAI1_RXD7DI, DIONVCC_3V3i.MX8M
73CIF_D8DI, DIONVCC_3V3i.MX8M
75CIF_D9DI, DIONVCC_3V3i.MX8M
77BACKLIGHT_PWMDO, DIONVCC_3V3i.MX8M
79SPIN79DI, DIONVCC_3V3i.MX8M
81SD2_DATA1DIONVCC_3V3i.MX8M
83GNDGround
85SD2_DATA2DIONVCC_3V3i.MX8M
87RESET_OUTDONVCC_3V3FPGA + i.MX8M + Kinetis MCU
89+3V3_AUX (NVCC_3V3)PO+3V3NVCC_3V3
91+3V3_AUX (NVCC_3V3)PO+3V3NVCC_3V3
93-
95SPIN95DIONVCC_3V3i.MX8M
97CAN1_RXDI, DIONVCC_3V3i.MX8M
99CAN1_TXDO, DIONVCC_3V3i.MX8M
101CAN2_RXDI, DIONVCC_3V3i.MX8M
103CAN2_TXDO, DIONVCC_3V3i.MX8M
105QSPI_SCLK (CS1)DO, DIONVCC_3V3i.MX8M
107QSPI_SS0 (CS3)DO, DIONVCC_3V3i.MX8M
109GNDGround
111QSPI_DATA0 (A00)DIONVCC_3V3i.MX8M
113QSPI_DATA1 (A01)DIONVCC_3V3i.MX8M
115PCIE_CLKREQDIONVCC_3V3i.MX8M
117QSPI_DATA2 (A03)DIONVCC_3V3i.MX8M
119QSPI_DATA3 (A04)DIONVCC_3V3i.MX8M
121SPIN121 (A05)DIONVCC_3V3i.MX8M
123CSI1_PWDNDO, DIONVCC_3V3i.MX8M
125CSI_RESETDO, DIONVCC_3V3i.MX8M
127USB1_PENDO, DIONVCC_3V3i.MX8M
129USB2_PENDO, DIONVCC_3V3i.MX8M
131USB2_OCDI, DIONVCC_3V3i.MX8M
133USB1_OCDI, DIONVCC_3V3i.MX8M
135USB1_VBUSDI (PO)+5Vi.MX8M
137USB1_IDDINVCC_3V3i.MX8M
139USB1_DPDDIONVCC_3V3i.MX8M
141USB1_DNDDIONVCC_3V3i.MX8M
143USB2_DPDDIONVCC_3V3i.MX8M
145USB2_DNDDIONVCC_3V3i.MX8M
147GNDGround
149HDMI_DDC_SDADIONVCC_3V3i.MX8M
151USB2_TX_PDDIONVCC_3V3i.MX8M
153USB2_TX_NDDIONVCC_3V3i.MX8M
155USB2_RX_PDDIONVCC_3V3i.MX8M
157USB2_RX_NDDIONVCC_3V3i.MX8M
159SPDIF_INDI, DIONVCC_3V3i.MX8M
161SPDIF_OUTDO, DIONVCC_3V3i.MX8M
163SPDIF_EXT_CLKDI, DIONVCC_3V3i.MX8M
165LED_WLDONVCC_3V3Wifi
167LED_BTDONVCC_3V3BT
169VDD_ENET_IOPOEthernet signal IO voltage
171ETH_LED_SPEED1000ODNVCC_3V3Gbit Ethernet-Phy
173ETH_TRX2_NDDIOVDD_ENET_IOGbit Ethernet-Phy
175ETH_TRX2_PDDIOVDD_ENET_IOGbit Ethernet-Phy
177ETH_TRX3_NDDIOVDD_ENET_IOGbit Ethernet-Phy
179ETH_TRX3_PDDIOVDD_ENET_IOGbit Ethernet-Phy
181GNDGround
183ETH_LED_LINK_AKTODNVCC_3V3Gbit Ethernet-Phy
185ETH_LED_SPEED100ODNVCC_3V3Gbit Ethernet-Phy
187ETH_TRX0_NDDIOVDD_ENET_IOGbit Ethernet-Phy
189ETH_TRX0_PDDIOVDD_ENET_IOGbit Ethernet-Phy
191ETH_GNDGround
193ETH_TRX1_NDDIOVDD_ENET_IOGbit Ethernet-Phy
195ETH_TRX1_PDDIOVD

2 Interfaces

This chapter includes a short description of all interfaces of the Trizeps VIII Plus. Please consult the processor datasheet for detailed information.

2.1 Power Supply​

The Trizeps VIII Plus can be supplied by a single +3V3/+5V power-supply. But it is possible to supply parts of the modules separately.

NameDescription
+3V3_SNVS+3V3 power input. This supply powers the Kinetis MCU, which controls reset and power to the i.MX8M processor and may be programmed by customers.
VSYSMain power input.
+3V3_AUX (NVCC_3V3)+3V3 output. NVCC_3V3 is the IO voltage for several peripherals of the i.MX8M Plus. GPIO states are undefined until +3V3_AUX is available.
AUDIO_VDD+3V3 power input for audio. Also used as reference voltage for the ADC of the Kinetis MCU.
AUDIO_VDD_SPEAKER+3V3 or +5V power input for audio speaker.
AUDIO_AGNDAnalog GND.
VDD_ENET_IO+2V5 power output. Ethernet signal IO voltage.
VDD_FPGA_MIPI+2V5 power output. Voltage is programmable and supplies the MIPI IO banks of the FPGA.
VSD_3V3SD signal IO voltage power output. ON/OFF switchable.

2.2 Control-Signals​

NameDescription
RESET_INNegated reset input. 0: reset device, 1: normal operation.
RESET_OUTNegated reset output. 0: device in reset, 1: normal operation.
SPIN24_CTS3Connected to the programmable Kinetis MCU; may be used to control ON/OFF or BOOT_MODE pin of i.MX8M.

2.3 UART​

The i.MX8M provides 4 Universal Asynchronous Receiver/Transmitter. With a transceiver these signals can be converted to RS232, RS485 or IrDA. The SODIMM200 standard defines 3 UART ports, but all 4 UARTs are accessible through the SODIMM200 connector if needed.

NameDescription
UART1_TXDUART1 transmit output
UART1_RXDUART1 receive input
UART1_RTSUART1 request to send output
UART1_CTSUART1 clear to send input
UART1_DTRUART1 data terminal ready output; a GPIO is used to emulate this function
UART1_DSRUART1 data set ready input; a GPIO is used to emulate this function
UART1_DCDUART1 data carrier detect input; a GPIO is used to emulate this function
UART1_RIUART1 ring indicator input; a GPIO is used to emulate this function
UART2_TXDUART2 transmit output
UART2_RXDUART2 receive input
UART2_RTSUART2 request to send output. This pin can be configured to be UART4_RXD
UART2_CTSUART2 clear to send input. This pin can be configured to be UART4_TXD
UART3_TXDUART3 transmit output; routed through the FPGA. If Trizeps module is without FPGA, it can be routed to SODIMM or BT-module
UART3_RXDUART3 receive input; routed through the FPGA. If Trizeps module is without FPGA, it can be routed to SODIMM or BT-module
SPIN22_RTS3UART3 request to send output; routed through the FPGA. If Trizeps module is without FPGA, can be routed to SODIMM or BT-module. SODIMM200 does not specify a RTS-pin for UART3
SPIN24_CTS3UART3 clear to send input; routed through the FPGA. If Trizeps module is without FPGA, can be routed to SODIMM or BT-module. SODIMM200 does not specify a CTS-pin for UART3

Baudrate: High-speed TIA/EIA-232-F compatible, up to 1Mbit/s IrDA-compatible, up to 115.2 Kbit/s Data-Bits: 7 or 8 bits (RS232) or 9 bit (RS485) Stop-Bits: 1, 2 Parity: None, Even, Odd Features: Hardware-flow-control (RTS,CTS)

2.4 SPI​

The serial peripheral interface is a programmable synchronous serial port, which may be used to connect to a multiple of different peripherals. The i.MX8M features an Enhanced Configurable SPI (ECSPI). The ECSPI2 is routed to the Kinetis MCU and to the FPGA. The FPGA allows to route these signals to pins, that carried the SPI pins on previous Trizeps SODIMM200 modules. If no FPGA is mounted, there is a mounting option to route these signals to FPGA_CIF_VSYNC, FPGA_CIF_HSYNC, FPGA_CIF_MCLK and FPGA_CIF_PCLK.

NameDescription
SPI2_SS0SPI2 Slave Select
SPI2_SCLKSPI2 Clock
SPI2_MISOSPI2 Master In Slave Out
SPI2_MOSISPI2 Master Out Slave In

Speed: up to 52Mbit/s Features: Master & Slave mode

2.5 QSPI​

The Quad Serial Peripheral Interface (QuadSPI) is a synchronous serial port with up to four bidirectional data lines to interface with external serial flash devices. This interface is not part of the SODIMM200 standard.

NameDescription
QSPI_SS0Quad SPI Slave Select
QSPI_SCLKQuad SPI Clock
QSPI_DATA0Quad SPI Data0
QSPI_DATA1Quad SPI Data1
QSPI_DATA2Quad SPI Data2
QSPI_DATA3Quad SPI Data3

Speed: up to 50MHz Features: Master only.

2.6 I2C​

The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave.

NameDescription
I2C2_SCLPrimary I2C; Clock
I2C2_SDAPrimary I2C; Data
I2C1_SCLSecondary I2C; Clock
I2C1_SDASecondary I2C; Data

Speed: Standard mode, up to 100 kbit/s Fast mode, up to 400 kbit/s Features: Multimaster operation. I2C Bus Specification Version 2.1

2.7 I2S​

The Inter-IC sound interface provides a synchronous audio interface (SAI) and is used to connect to audio codecs. This interface is not part of the SODIMM200 standard.

NameDescription
SAI1_TXCTransmit Bit Clock
SAI1_TXFSTransmit Frame Sync
SAI1_TXD0Serial transmit data channel 0
SAI1_TXD1Serial transmit data channel 1
SAI1_TXD2Serial transmit data channel 2
SAI1_TXD3Serial transmit data channel 3
SAI1_TXD4Serial transmit data channel 4
SAI1_TXD5Serial transmit data channel 5
SAI1_TXD6Serial transmit data channel 6
SAI1_TXD7Serial transmit data channel 7
SAI1_RXCReceive Bit Clock
SAI1_RXFSReceive Frame Sync
SAI1_MCLKAudio Master Clock
SAI1_RXD0Serial receive data channel 0
SAI1_RXD1Serial receive data channel 1
SAI1_RXD2Serial receive data channel 2
SAI1_RXD3Serial receive data channel 3
SAI1_RXD4Serial receive data channel 4
SAI1_RXD5Serial receive data channel 5
SAI1_RXD6Serial receive data channel 6
SAI1_RXD7Serial receive data channel 7
BT_PCM_CLKBT PCM clock (SAI3_RXC), optional connected to BT-module
BT_PCM_SYNCBT PCM Sync (SAI3_RXFS), optional connected to BT-module
BT_PCM_INBT PCM In (SAI3_TXD), optional connected to BT-module
BT_PCM_OUTBT PCM Out (SAI3_RXD), optional connected to BT-module

2.8 SD-Card​

The SD-Card Interface may be used to connect a SD-Card, eMMC or SDIO-hardware to the Trizeps module.

NameDescription
SD2_CMDSD-card command output
SD2_CLKSD-card clock output
SD2_DAT0SD-card data bit 0
SD2_DAT1SD-card data bit 1
SD2_DAT2SD-card data bit 2
SD2_DAT3SD-card data bit 3
SD2_DETSD-card detect: 1 = card inserted, 0 = card removed

Speed: Card bus clock frequency up to 208 MHz Features: Conforms to the SD Host Controller Standard Specification version 3.0 Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/5.0 Compatible with the SD Memory Card Specification version 3.0 and supports the Extended Capacity SD Memory Card Compatible with the SDIO Card Specification version 3.0

2.9 USB​

The Trizeps VIII Plus got two super-speed USB 3.0 ports (1 x OTG, 1 x Host).

NameDescription
USB1_DPUSB1 Data Plus
USB1_DNUSB1 Data Negative
USB1_RX_PUSB1 Receive Data Plus
USB1_RX_NUSB1 Receive Data Negative
USB1_TX_PUSB1 Transmit Data Plus
USB1_TX_NUSB1 Transmit Data Negative
USB1_PENUSB1 Power Enable output
USB1_OCUSB1 Overcurrent Detect input
USB1_VBUSUSB1 VBUS (+5V)
USB1_IDUSB1 ID Detect
USB2_DPUSB2 Data Plus
USB2_DNUSB2 Data Negative
USB2_RX_PUSB2 Receive Data Plus
USB2_RX_NUSB2 Receive Data Negative
USB2_TX_PUSB2 Transmit Data Plus
USB2_TX_NUSB2 Transmit Data Negative
USB2_PENUSB2 Power Enable output
USB2_OCUSB2 Overcurrent Detect input

Speed: Super-speed 4 Gbit/s High-speed 480 Mbit/s Full-speed 12 Mbit/s Low-speed 1.5 Mbit/s Features: Complies with USB specification rev 3.0 (xHCI compatible)

2.10 PCIe​

The i.MX8M Plus features one PCI Express dual mode (DM) controller. The PCIe port is connected to the internal Wireless module. On modules without Wireless the signals are available on the SODIMM200 connector.

NameDescription
PCIE_REFCLK_NPCIE Clock (negative)
PCIE_REFCLK_PPCIE Clock (positive)
PCIE_TXN_NPCIE Transmit Data (negative)
PCIE_TXN_PPCIE Transmit Data (positive)
PCIE_RXN_NPCIE Receive Data (negative)
PCIE_RXN_PPCIE Receive Data (positive)
PCIE_WAKEPCIE Wake signal
PCIE_CLKREQPCIE Clock Request signal

Speed: 1.5 / 2.5 / 3.0 / 5.0 / 6.0 Gbps Features: PCIe specification Gen2 x1 lane PCI Express 1.1/2.0 standard PCI Express Base Specification, Revision 4.0, Version 0.7 PIPE Specification for PCI Express, Version 4.3 PCI Local Bus Specification, Revision 3.0 PCI Bus Power Management Specification, Revision 1.2

2.11 Ethernet​

The Trizeps VIII Plus uses an Realtek RTL8211 integrated 10/100/1000 Mbps Ethernet Transceiver to interface with the i.MX8M Plus RGMII.

NameDescription
ETH_TRX0_NEthernet0 Transmit/Receive Data 0 (negative)
ETH_TRX0_PEthernet0 Transmit/Receive Data 0 (positive)
ETH_TRX1_NEthernet0 Transmit/Receive Data 1 (negative)
ETH_TRX1_PEthernet0 Transmit/Receive Data 1 (positive)
ETH_TRX2_NEthernet0 Transmit/Receive Data 2 (negative)
ETH_TRX2_PEthernet0 Transmit/Receive Data 2 (positive)
ETH_TRX3_NEthernet0 Transmit/Receive Data 3 (negative)
ETH_TRX3_PEthernet0 Transmit/Receive Data 3 (positive)
ETH_LED_LINK_AKTLED output for 10/100/1000 BASE-T activity
ETH_LED_SPEED100LED output for 10 / 100 BASE-T link
ETH_LED_SPEED1000LED output for 1000 BASE-T link
VDD_ENET_IO+2V5 IO-voltage output

An additional 10/100/1000 Mbps Ethernet interface is accessible via RGMII signals, routed directly to the SODIMM200.

NameDescription
ENET1_TX_CTLEthernet1 Transmit Control
ENET1_TXCEthernet1 Transmit Clock
ENET1_TD0Ethernet1 Transmit Data 0
ENET1_TD1Ethernet1 Transmit Data 1
ENET1_TD2Ethernet1 Transmit Data 2
ENET1_TD3Ethernet1 Transmit Data 3
ENET1_RX_CTLEthernet1 Receive Control
ENET1_RXCEthernet1 Receive Clock
ENET1_RD0Ethernet1 Receive Data 0
ENET1_RD1Ethernet1 Receive Data 1
ENET1_RD2Ethernet1 Receive Data 2
ENET1_RD3Ethernet1 Receive Data 3

2.12 CAN​

The CAN interface of The Trizeps VIII Plus supports 2 x CAN FD.

NameDescription
CAN1_RXCAN1 Receive Data
CAN1_TXCAN1 Transmit Data
CAN2_RXCAN2 Receive Data
CAN2_TXCAN2 Transmit Data

2.13 Display​

The i.MX8M processor has this display interfaces:

  • DSI-MIPI (4ch)

  • Dual Channel LVDS

The DSI-MIPI interface can be converted to parallel RGB Display ( through on board FPGA)

NameDescription
DISPLAY_ENABLEThis GPIO is typically used to control the display-enable signal of an attached display.
BACKLIGHT_PWMThis GPIO is capable of generating a PWM and is typically used to generate the backlight PWM signal.

2.13.1 DSI-MIPI (4ch)​

The DSI-MIPI signals are routed to an FPGA and to the B2B-connector.

NameDescription
LVDS0_CLK_PChannel A LVDS Clock (positive)
LVDS0_CLK_NChannel A LVDS Clock (negative)
LVDS0_TX0_PChannel A LVDS Data 0 (positive)
LVDS0_TX0_NChannel A LVDS Data 0 (negative)
LVDS0_TX1_PChannel A LVDS Data 1 (positive)
LVDS0_TX1_NChannel A LVDS Data 1 (negative)
LVDS0_TX2_PChannel A LVDS Data 2 (positive)
LVDS0_TX2_NChannel A LVDS Data 2 (negative)
LVDS0_TX3_PChannel A LVDS Data 3 (positive)
LVDS0_TX3_NChannel A LVDS Data 3 (negative)
LVDS1_CLK_PChannel B LVDS Clock (positive)
LVDS1_CLK_NChannel B LVDS Clock (negative)
LVDS1_TX0_PChannel B LVDS Data 0 (positive)
LVDS1_TX0_NChannel B LVDS Data 0 (negative)
LVDS1_TX1_PChannel B LVDS Data 1 (positive)
LVDS1_TX2_PChannel B LVDS Data 2 (positive)
LVDS1_TX2_NChannel B LVDS Data 2 (negative)
LVDS1_TX3_PChannel B LVDS Data 3 (positive)
LVDS1_TX3_NChannel B LVDS Data 3 (negative)

Speed: Support 80Mbps – 1.5Gbps data rate in high speed operation Support 10Mbps data rate in low power operation. Features: Compliant to MIPI-DSI standard v1.2

2.13.2 Single-/Dual LVDS​

The Trizeps VIII Plus supports Single- and Dual-LVDS up to FullHD (1080p)

NameDescription
LVDS0_CLK_PChannel A LVDS Clock (positive)
LVDS0_CLK_NChannel A LVDS Clock (negative)
LVDS0_TX0_PChannel A LVDS Data 0 (positive)
LVDS0_TX0_NChannel A LVDS Data 0 (negative)
LVDS0_TX1_PChannel A LVDS Data 1 (positive)
LVDS0_TX1_NChannel A LVDS Data 1 (negative)
LVDS0_TX2_PChannel A LVDS Data 2 (positive)
LVDS0_TX2_NChannel A LVDS Data 2 (negative)
LVDS0_TX3_PChannel A LVDS Data 3 (positive)
LVDS0_TX3_NChannel A LVDS Data 3 (negative)
LVDS1_CLK_PChannel B LVDS Clock (positive)
LVDS1_CLK_NChannel B LVDS Clock (negative)
LVDS1_TX0_PChannel B LVDS Data 0 (positive)
LVDS1_TX0_NChannel B LVDS Data 0 (negative)
LVDS1_TX1_PChannel B LVDS Data 1 (positive)
LVDS1_TX2_PChannel B LVDS Data 2 (positive)
LVDS1_TX2_NChannel B LVDS Data 2 (negative)
LVDS1_TX3_PChannel B LVDS Data 3 (positive)
LVDS1_TX3_NChannel B LVDS Data 3 (negative)

2.13.3 Parallel RGB Display​

The Trizeps VIII Plus can be equipped with a Lattice MachXO3 FPGA with up to 4300LUT. This FPGA may be programmed to convert the MIPI-DSI data stream into parallel display output. Although this allows flexible pinning, it is recommended to follow the Trizeps SODIMM200 standard.

NameDescription
FPGA_LCD_PCLKPixel-Clock
FPGA_LCD_DEData-Enable / Data-Valid
FPGA_LCD_HSYNCHorizontal Sync
FPGA_LCD_VSYNCVertical Sync
FPGA_LCD_D00blue [0]
FPGA_LCD_D01blue [1]
FPGA_LCD_D02blue [2]
FPGA_LCD_D03blue [3]
FPGA_LCD_D04blue [4]
FPGA_LCD_D0524bpp: blue [5]; 18bpp: blue [5]; 16bpp: green [0]
FPGA_LCD_D0624bpp: blue [6]; 18bpp: green [0]; 16bpp: green [1]
FPGA_LCD_D0724bpp: blue [7]; 18bpp: green [1]; 16bpp: green [2]
FPGA_LCD_D0824bpp: green [0]; 18bpp: green [2]; 16bpp: green [3]
FPGA_LCD_D0924bpp: green [1]; 18bpp: green [3]; 16bpp: green [4]
FPGA_LCD_D1024bpp: green [2]; 18bpp: green [4]; 16bpp: green [5]
FPGA_LCD_D1124bpp: green [3]; 18bpp: green [5]; 16bpp: red [0]
FPGA_LCD_D1224bpp: green [4]; 18bpp: red [0]; 16bpp: red [1]
FPGA_LCD_D1324bpp: green [5]; 18bpp: red [1]; 16bpp: red [2]
FPGA_LCD_D1424bpp: green [6]; 18bpp: red [2]; 16bpp: red [3]
FPGA_LCD_D1524bpp: green [7]; 18bpp: red [3]; 16bpp: red [4]
FPGA_LCD_D1624bpp: red [0]; 18bpp: red [4]
FPGA_LCD_D1724bpp: red [1]; 18bpp: red [5]
FPGA_LCD_D1824bpp: red [2]
FPGA_LCD_D1924bpp: red [3]
FPGA_LCD_D2024bpp: red [4]
FPGA_LCD_D2124bpp: red [5]
FPGA_LCD_D2224bpp: red [6]
FPGA_LCD_D2324bpp: red [7]

1.13.4 HDMI​

The HDMI signals are routed to the B2B-connector and the SODIMM.

NameDescription
HDMI_CLKPHDMI Clock (positive)
HDMI_CLKNHDMI Clock (negative)
HDMI_TX0PHDMI Data 0 (positive)
HDMI_TX0NHDMI Data 0 (negative)
HDMI_TX1PHDMI Data 1 (positive)
HDMI_TX1NHDMI Data 1 (negative)
HDMI_TX2PHDMI Data 2 (positive)
HDMI_TX2NHDMI Data 2 (negative)
HDMI_DDC_SCLHDMI Control Interface Clock
HDMI_DDC_SDAHDMI Control Interface Data
HDMI_HPDHDMI Hot Plug Detection
HDMI_CECHDMI Consumer Electronics Control

2.14 Camera​

The i.MX8M Plus Processor got two MIPI CSI camera interfaces. They are connected to the B2B-connector.

NameDescription
MIPI_CSI1_CLK_NFirst camera clock input – negative
MIPI_CSI1_CLK_PFirst camera clock input – positive
MIPI_CSI1_D0_NFirst camera data lane 0 – negative
MIPI_CSI1_D0_PFirst camera data lane 0 – positive
MIPI_CSI1_D1_NFirst camera data lane 1 – negative
MIPI_CSI1_D1_PFirst camera data lane 1 – positive
MIPI_CSI1_D2_NFirst camera data lane 2 – negative
MIPI_CSI1_D2_PFirst camera data lane 2 – positive
MIPI_CSI1_D3_NFirst camera data lane 3 – negative
MIPI_CSI1_D3_PFirst camera data lane 3 – positive
MIPI_CSI2_CLK_NSecond camera clock input – negative
MIPI_CSI2_CLK_PSecond camera clock input – positive
MIPI_CSI2_D0_NSecond camera data lane 0 – negative
MIPI_CSI2_D1_NSecond camera data lane 1 – negative
MIPI_CSI2_D1_PSecond camera data lane 1 – positive
MIPI_CSI2_D2_NSecond camera data lane 2 – negative
MIPI_CSI2_D2_PSecond camera data lane 2 – positive
MIPI_CSI2_D3_NSecond camera data lane 3 – negative
MIPI_CSI2_D3_PSecond camera data lane 3 – positive

Speed: Support 80Mbps – 1.5Gbps data rate in high speed operation Support 10Mbps data rate in low power operation. Features: up to 4-lane; 1.5 Gbps per lane, Support up to 1080p@60fps video capture.

NameDescription
CSI1_PWDNThis GPIO is typically used to control the Power-Down pin of a camera.
CSI_RESETThis GPIO is typically used to control the Reset pin of a camera.

2.15 Wireless​

The Trizeps VIII Plus may be equipped with a HD Wireless SPB228, Silex SX- PCEAC2 or AzureWave CM276NF module. The antennas are connected directly to the module.

NameDescription
BT_LEDBT active LED

2.16 Audio​

The Trizeps VIII Plus uses a WM8962 audio-codec. (Other codec-options available on request)

NameDescription
AUDIO_MIC_OUTMain mic input
AUDIO_MIC_GNDMicrophone ground
AUDIO_LINEIN_LLineIn left channel input
AUDIO_LINEIN_RLineIn right channel input
AUDIO_HEADPHONE_LHeadphone left channel output
AUDIO_HEADPHONE_RHeadphone right channel output
AUDIO_HEADPHONE_GNDHeadphone ground sensing input
SPEAKER_PClass-D speaker amp + output
SPEAKER_NClass-D speaker amp – output
AUDIO_ENABLEGPIO typically used to control the enable pin of an external audio-amplifier connected to the AUDIO_HEADPHONE pins

2.17 SPDIF​

The i.MX8M Plus supplies a Sony/Philips Digital Interface (SPDIF) stereo transceiver that allows the processor to receive and transmit digital audio.

NameDescription
SPDIF_INSPDIF input
SPDIF_OUTSPDIF output
SPDIF_EXT_CLKSPDIF clock

2.18 Secure Element​

The Trizeps VIII Plus supports a built-in Secure Element solution consisting of a NXP SE050 which is connected to I2C3.

3 Specifications

3.1 Absolute Maximum Ratings​

Absolute maximum ratings reflect conditions that the module may be exposed outside of the operating limits, without experiencing immediate functional failure. Functional operation is only expected during the conditions indicated under "Recommended Operating Conditions". Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the module. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

PinMinMaxUnit
Supply Voltage (+3V3_SNVS / VSYS / AUDIO_VDD / AVDD_SPEAKER)-0.3 / -0.3 / -0.3 / -0.33.8 / 5.5 / 4.5 / 7.0V / V / V / V
Storage Temperature (TStorage)-40+85°C
PinMinTypMaxUnit
Supply Voltage (3V3_SNVS / VSYS / AUDIO_VDD / AVDD_SPEAKER)3.1 / 3.1 / 2.8 / 2.83.3 / 3.3 / 3.3 / 3.33.4 / 5.0 / 3.4 / 5.0V / V / V / V
Supply current (typ.) - usage depends on processor, GPU, display, peripherals, battery. Recommended: 2A regulator416 / 757 / 1151456.5 / 824522 / 923mA / mA / mA / A
Operating temperature (TConsumer / TExtended / TIndustrial) - max i.MX 8M Plus: +95°C consumer, +105°C industrial. High refresh-rate recommended if LPDDR4 >85°C. eMMC temp affects Data Retention0 / -25 / -40+25 / +25 / +25+85 / +85 / +85°C / °C / °C

3.3 ESD Ratings​

ParameterMaxUnit
V(ESD) Electrostatic dischargeHuman body model (HBM) ±1000 Charged-device model (CDM) ±250V

3.4 Electrical Characteristics​

3.4.1 i.MX 8M Plus GPIO DC parameters. Please view i.MX 8M Plus datasheet​

for details:

ParameterDescriptionMinMaxUnit
VIL_3V3Low-level input voltage-0.30.3 x VDDV
VIH_3V3High-level input voltage0.7 x VDDVDD + 0.3V
VOH_3V3High-level output voltage0.8 x VDDVDDV
VOL_3V3Low-level output voltage00.2 x VDDV
RP_upPull-Up Resistance (1)1872kΩ
RP_downPull-Down Resistance (1)2487kΩ

  • The i.MX 8M Plus does not support internal pull-up/down for VDD=3.3V.

  • The state of the GPIO-pins is undefined until the PMIC has powered-up and +3V3_AUX is supplied.

3.4.2 FPGA single-Ended DC parameters. Please view FPGA datasheet for​

details:

ParameterDescriptionMinMaxUnit
VIL_3V3Low-level input voltage-0.30.8V
VIH_3V3High-level input voltage2.03.6V
VOH_3V3High-level output voltageVSYS–0.2 (IOH=-100µA), VSYS-0.4 (IOH=-16mA)-V
VOL_3V3Low-level output voltage-0.2 (IOL=100µA), 0.4 (IOL=16mA)V
IPUPull-Up Current-30-309µA
IPDPull-Down Current30305µA

3.4.3 Cortex M0+ MCU DC parameters. Please view MCU datasheet for details:​

ParameterDescriptionMinMaxUnit
VIL_3V3Low-level input voltage-0.35 × VCC_SNVSV
VIH_3V3High-level input voltage0.7 × VCC_SNVS-V
VOH_3V3High-level output voltageVSYS–0.5 (IOH=-5mA), VSYS-0.5 (IOH=-18mA)-V
VOL_3V3Low-level output voltage-0.5 (IOL=5mA), 0.5 (IOL=18mA)V
IOHTOutput high current total for all ports-100mA
IOLTOutput low current total for all ports-100mA
RPUInternal pullup resistor2050kΩ

3.5 Mechanical Specification​

Dimensions (mm) of the Trizeps VIII Plus module (top view)

Dimensions (mm) of the Trizeps VIII Plus module (bottom view)

4 Article numbers for Trizeps VIII Plus

Part number structure

Examples article numbers

Article number 00…Trizeps VIII Plus
66B21.E0912.H00S00Trizeps VIII Plus EC/Quad/IT1600/R2G/EMMC8G/ETH/COD/RoHS (Extended Consumer Temperature -25 to 85°C, i.MX 8M Plus Quad Core, IT 1.6 GHz, 2 GB RAM, 8 GB eMMC, Ethernet, Codec)
66A21.C2B32.H00S00Trizeps VIII Plus CT/Quad/C01800/R2G/EMMC8G/FPGA/ETH/COD/MCU/WB/RoHS (Consumer Temperature 0 to 70°C, i.MX 8M Plus Quad Core, C0 1.8 GHz, 2 GB RAM, 8 GB eMMC, FPGA LF21, Ethernet, Codec, Kinetis MCU, WLAN, BT)

Other versions on request

5 Important Notice

6 Document History

Rev.DateAuthorChanges
0.908.03.2022JPInitial version
0.9.124.05.2022VoBChapter 4.0 adjusted
0.9.208.06.2022JPMinor changes
1.021.11.2022MPUpdate new CI

Baseboard & Panels​

The Trizeps VIII Plus fits into following Seco products: